| Patents for G06F 7 - Methods or arrangements for processing data by operating upon the order or content of the data handled (93,043) |
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| 04/18/1995 | US5408632 Semiconductor memory having a bit position decoder and date re-ordering circuitry for arranging bits in a word of data |
| 04/18/1995 | US5408436 Circuit structure having distributed registers with self-timed reading and writing operations |
| 04/18/1995 | US5408427 Detection of exponent underflow and overflow in a floating point adder |
| 04/18/1995 | US5408426 Arithmetic unit capable of performing concurrent operations for high speed operation |
| 04/13/1995 | WO1995006918A3 Real-time automated trading system |
| 04/13/1995 | WO1995000896A3 Method and apparatus for indexing searching and displaying data |
| 04/11/1995 | US5406506 Domino adder circuit having MOS transistors in the carry evaluating paths |
| 04/11/1995 | US5406247 Median value detection technique |
| 04/06/1995 | WO1995007015A3 Method and apparatus of combining signals in a digital pipelined signal adder |
| 04/06/1995 | DE4401064C1 Circuit arrangement for modulation, demodulation, coordinate transformation or angle measurement |
| 04/05/1995 | EP0646860A1 Full adder circuit |
| 04/04/1995 | US5404551 Parallel processor which processes instructions, after a branch instruction, in parallel prior to executing the branch instruction and its parallel processing method |
| 04/04/1995 | US5404447 Apparatus for manipulating image pixel streams to generate an output image pixel stream in response to a selected mode |
| 04/04/1995 | US5404324 Methods and apparatus for performing division and square root computations in a computer |
| 04/04/1995 | US5404323 Pipelined multiplier for signed multiplication |
| 03/30/1995 | DE4332673A1 Multiplication circuit |
| 03/29/1995 | EP0645775A1 Electronic sequential access memory circuit |
| 03/29/1995 | EP0645699A1 Fast multiply-add instruction sequence in a pipeline floating-point processor |
| 03/29/1995 | EP0645698A1 Circuitry for generating a quotient |
| 03/29/1995 | EP0645697A1 Minimum shift data arranging method and apparatus |
| 03/29/1995 | EP0645046A1 Data writing to non-volatile memory |
| 03/28/1995 | WO1995009391A1 Minimum value/maximum value retrieving apparatus |
| 03/28/1995 | US5402369 Method and apparatus for digital multiplication based on sums and differences of finite sets of powers of two |
| 03/28/1995 | US5402368 Computing unit and digital signal processor using the same |
| 03/28/1995 | US5402122 TPC radix converter |
| 03/28/1995 | US5402012 Sequentially clocked domino-logic cells |
| 03/23/1995 | WO1995005633A3 Carry-look-ahead adder with reduces number of stages |
| 03/22/1995 | EP0644480A2 Multiple resonant tunneling circuits for positive digit multi-valued logic operations |
| 03/22/1995 | EP0644479A2 Multiple resonant tunneling circuits for signed digit multi-valued logic operations |
| 03/22/1995 | CN1100541A Neural network and method of using same |
| 03/21/1995 | US5400272 Diagonal propagation digital multiplier |
| 03/21/1995 | US5400271 Apparatus for and method of calculating sum of products |
| 03/21/1995 | US5400007 Multiple level parallel magnitude comparator |
| 03/21/1995 | US5399919 Apparatus for detecting switch actuation |
| 03/16/1995 | DE4406391C1 Electronic computing unit (arithmetic unit) |
| 03/15/1995 | EP0643489A1 Binary converter |
| 03/15/1995 | EP0643352A1 Self-checking complementary adder unit |
| 03/14/1995 | US5398328 System for obtaining correct byte addresses by XOR-ING 2 LSB bits of byte address with binary 3 to facilitate compatibility between computer architecture having different memory orders |
| 03/14/1995 | US5398319 Microprocessor having apparatus for dynamically controlling a kind of operation to be performed by instructions to be executed |
| 03/14/1995 | US5398270 Data coincidence detecting circuit |
| 03/14/1995 | US5398245 Packet processing method and apparatus |
| 03/14/1995 | US5398198 Single integrated circuit having both a memory array and an arithmetic and logic unit (ALU) |
| 03/09/1995 | WO1995007015A2 Method and apparatus of combining signals in a digital pipelined signal adder |
| 03/09/1995 | WO1995006979A1 Logic structure and circuit for fast carry |
| 03/09/1995 | WO1995006918A2 Real-time automated trading system |
| 03/09/1995 | WO1995006906A1 Method and apparatus for encryption having a feedback register with selectable taps |
| 03/08/1995 | EP0642093A2 Method and apparatus for automatically designing a multiplier circuit |
| 03/07/1995 | US5396641 Reconfigurable memory processor |
| 03/07/1995 | US5396622 Efficient radix sorting system employing a dynamic branch table |
| 03/07/1995 | US5396502 Single-stack implementation of a Reed-Solomon encoder/decoder |
| 03/07/1995 | US5396445 Binary carry-select adder |
| 03/07/1995 | US5396236 Converting method of vertical data/horizontal data and a circuit therefor |
| 03/02/1995 | DE4406395C1 Signal processing method for the multiplication of input signals by parameters and for subsequent accumulation |
| 03/01/1995 | EP0640912A1 Memory addressing scheme for increasing the number of memory locations available in a computer for storing higher precision numbers |
| 02/28/1995 | US5394405 Universal weight generator |
| 02/28/1995 | US5394352 Carry lookahead circuit for semiconductor integrated circuit |
| 02/28/1995 | US5394351 Optimized binary adder and comparator having an implicit constant for an input |
| 02/28/1995 | US5394350 Square computation circuit |
| 02/23/1995 | WO1995005633A2 Carry-look-ahead adder with reduces number of stages |
| 02/23/1995 | DE4326988A1 Method for controlling machine tools |
| 02/22/1995 | EP0639909A1 Resequencing system |
| 02/22/1995 | EP0639907A1 Digital signature method and key agreement method |
| 02/22/1995 | EP0639816A2 Field programmable digital signal processing array integrated circuit |
| 02/22/1995 | EP0626084A4 Integrated circuit computing device comprising dynamically configurable gate array having a reconfigurable execution means. |
| 02/22/1995 | EP0267271B1 In-system programmable logic device |
| 02/21/1995 | US5392423 Universal pipeline latch for mousetrap logic circuits |
| 02/21/1995 | US5392405 Data processor for detecting identical data coexisting in a plurality of data sections of data transmission paths |
| 02/21/1995 | US5392366 Pattern recognition apparatus |
| 02/21/1995 | US5392228 Result normalizer and method of operation |
| 02/21/1995 | US5391942 Clock distribution scheme for user-programmable logic array architecture |
| 02/18/1995 | CA2130234A1 Resequencing system |
| 02/16/1995 | WO1995004964A1 Modified wallace-tree adder for high-speed binary multiplier, structure and method |
| 02/16/1995 | WO1995001685A3 Method for cryptographic authentication of transmitted messages using pseudorandom numbers |
| 02/15/1995 | EP0638859A2 Signal processing device |
| 02/15/1995 | EP0541685B1 Associative memory |
| 02/14/1995 | US5390358 Data processing apparatus |
| 02/14/1995 | US5390137 Carry transfer apparatus |
| 02/14/1995 | US5390136 Artificial neuron and method of using same |
| 02/14/1995 | US5390135 Parallel shift and add circuit and method |
| 02/14/1995 | US5390134 System and method for reducing latency in a floating point processor |
| 02/14/1995 | US5389838 Device and method of managing asynchronous events in a finite state machine |
| 02/14/1995 | US5389835 Vector logic method and dynamic mousetrap logic gate for a self-timed monotonic logic progression |
| 02/14/1995 | CA2039639C Data dependency collapsing hardware apparatus |
| 02/09/1995 | WO1995004417A1 Restricted blind signatures |
| 02/09/1995 | WO1995004402A1 Microprocessor-based fpga |
| 02/09/1995 | CA2168658A1 Restricted blind signatures |
| 02/08/1995 | EP0637797A1 Calculation apparatus |
| 02/08/1995 | EP0329789B1 Galois field arithmetic unit |
| 02/07/1995 | US5388234 Finite state automation text search apparatus having two-level memory structure |
| 02/07/1995 | US5387768 Elevator passenger detector and door control system which masks portions of a hall image to determine motion and court passengers |
| 02/01/1995 | EP0636955A1 Control unit for vehicle and total control system therefor |
| 01/31/1995 | US5386583 High performance sort hardware accelerator in a data processing system including a plurality of comparator modules |
| 01/31/1995 | US5386578 Method for sorting and merging in a data processing system using a matrix of cells |
| 01/31/1995 | US5386534 Data processing system for generating symmetrical range of addresses of instructing-address-value with the use of inverting sign value |
| 01/31/1995 | US5386528 Address translator having a high speed data comparator |
| 01/31/1995 | US5386377 Parallelized borrow look ahead subtractor |
| 01/31/1995 | US5386376 Method and apparatus for overriding quotient prediction in floating point divider information processing systems |
| 01/31/1995 | US5386375 Floating point data processor and a method for performing a floating point square root operation within the data processor |
| 01/31/1995 | US5386156 Programmable function unit with programmable fast ripple logic |
| 01/25/1995 | EP0635782A1 Method and system for address access |