| Patents for G06F 7 - Methods or arrangements for processing data by operating upon the order or content of the data handled (93,043) |
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| 04/12/1994 | US5303176 High performance array multiplier using four-to-two composite counters |
| 04/12/1994 | US5303175 Floating point arithmetic unit |
| 04/12/1994 | US5303174 Floating pointing arithmetic operation system |
| 04/06/1994 | EP0590933A2 Sorting processor |
| 04/06/1994 | EP0590914A2 Microprocessor branch decision circuit |
| 04/06/1994 | EP0590251A2 High-speed adder |
| 04/06/1994 | EP0541684B1 Bit storage cell |
| 04/06/1994 | CN1084985A Addition and subtraction arithmetic unit suitable for multi carry system code |
| 04/05/1994 | US5301345 Data processing system for performing a shifting operation and a constant generation operation and method therefor |
| 04/05/1994 | US5301344 Multibus sequential processor to perform in parallel a plurality of reconfigurable logic operations on a plurality of data sets |
| 04/05/1994 | US5301341 Overflow determination for three-operand alus in a scalable compound instruction set machine which compounds two arithmetic instructions |
| 04/05/1994 | US5301338 System including central processing unit |
| 04/05/1994 | US5301139 Shifter circuit for multiple precision division |
| 04/05/1994 | US5301138 Device and method for evaluating logarithms |
| 04/05/1994 | US5301137 Circuit for fixed point or floating point arithmetic operations |
| 03/31/1994 | WO1993022720A3 Process for finding the reciprocal of a divisor by stepwise approximation |
| 03/31/1994 | DE4232471A1 Digital electronic circuit for addition subtraction multiplication and division - has tetrade circuit for addition and subtraction, and adder operated in switched mode together with shift registers operated by pulse generator |
| 03/31/1994 | DE4230310A1 Digital electronic circuit for multiplication, division, addition and subtraction - has switched tetrade circuit, shift registers combined with adder, and resets flip=flops by operation of key |
| 03/31/1994 | DE4229625A1 Digital electronic arithmetic circuit for addition subtraction multiplication and division - has adder stage combined with registers and single control unit providing control pulses |
| 03/31/1994 | DE4228747A1 Digital electronic arithmetic circuit for addition, subtraction, multiplication and division - has adder circuit together with shift registers control unit and registers with inputs from mode select buttons |
| 03/31/1994 | DE4228019A1 Digital electronic arithmetic circuit for addition, subtraction, multiplication and addition - has tetrade circuit for addition and subtraction, and circuit triggered by point shift registers without up-down pulse counter |
| 03/31/1994 | DE4226060A1 Digital electronic circuit for addition, subtraction, multiplication and division - has tetrade circuit for addition and subtraction, and additional circuit for supply of clock signal for shift registers when processing numbers with decimal point |
| 03/31/1994 | DE4224907A1 Digital electronic circuit for addition, subtraction, multiplication and division - has tetrade circuitry for addition and subtraction, and always clocks in first number into same shift register |
| 03/31/1994 | DE4224521A1 Digital arithmetic electronic circuit for addition, subtraction, multiplication and division - has adder circuit together with shift registers and control circuit generating pulses for all registers |
| 03/31/1994 | DE4223665A1 Electronic processing circuit with different processing modes - with additional pulse circuit having second input allowing clock control |
| 03/30/1994 | EP0589148A1 Multiplexer circuit for modified booth's multiplier or the like |
| 03/29/1994 | US5299319 High performance interlock collapsing SCISM ALU apparatus |
| 03/29/1994 | US5299283 Semiconductor device for executing fuzzy inference and method of operation thereof |
| 03/29/1994 | US5299262 Method for exponentiating in cryptographic systems |
| 03/29/1994 | US5299145 Adder for reducing carry processing |
| 03/22/1994 | US5297151 Adjustable weighted random test pattern generator for logic circuits |
| 03/22/1994 | US5297073 Integer divide using shift and subtract |
| 03/22/1994 | US5297072 Square-root operating circuit adapted to perform a square-root at high speed and apply to both of binary signal and quadruple signal |
| 03/22/1994 | US5297070 Transform processing circuit |
| 03/22/1994 | CA2050799C Shift amount floating-point calculating circuit with a small amount of hardware and rapidly operable |
| 03/22/1994 | CA2025451C Method of and apparatus for data distribution |
| 03/22/1994 | CA1328025C Method and system for monitoring the number of available buffers |
| 03/17/1994 | WO1994006076A1 High performance mantissa divider |
| 03/17/1994 | WO1994006075A1 Method and apparatus for non-numeric character discrimination |
| 03/17/1994 | DE4230855A1 Electronic digital circuit for addition and subtraction - has shift register and four bit processing circuit operated by pulse generating control circuit for repeated operations |
| 03/17/1994 | DE4222620A1 Electronic digital circuit for multiplication and division - has gating circuit with a pair of shift registers for processing the decimal point position |
| 03/17/1994 | DE4222125A1 Digital electronic circuit for multiplication and division - uses number of shift register units for control of decimal point during processing |
| 03/16/1994 | EP0587286A1 Digital signal processing method and apparatus |
| 03/15/1994 | US5295256 Automatic storage of persistent objects in a relational schema |
| 03/15/1994 | US5295250 Microprocessor having barrel shifter and direct path for directly rewriting output data of barrel shifter to its input |
| 03/15/1994 | US5295229 Circuit and method for determining membership in a set during a fuzzy logic operation |
| 03/15/1994 | US5295198 Pattern identification by analysis of digital words |
| 03/15/1994 | US5295173 Frequency divider for dividing two input pulses |
| 03/15/1994 | US5295090 Logic structure and circuit for fast carry |
| 03/15/1994 | US5294911 Data comparator |
| 03/10/1994 | DE4321473A1 FIFO with data expansion-compression in binary steps - uses shifted counter outputs to control address generators for read=write |
| 03/09/1994 | EP0585619A2 Method of detecting zero condition of arithmetic or logical computation result, and circuit for same |
| 03/08/1994 | US5293623 Random access memory based buffer memory and associated method utilizing pipelined look-ahead reading |
| 03/08/1994 | US5293558 Multiplication, division and square root extraction apparatus |
| 03/08/1994 | US5293081 Driver circuit for output buffers |
| 03/03/1994 | DE4302830C1 Feedback shift register reproducing random sequences - has five stages, each consisting of D=flip=flop, and XOR gates in feedback logic as well as clock generator. |
| 03/02/1994 | EP0584265A1 Null convention speed independent logic |
| 03/01/1994 | US5291612 System for evaluating boolean expressions using total differential generating tree structured processing elements controlled by partial subfunction differentials |
| 03/01/1994 | US5291431 Array multiplier adapted for tiled layout by silicon compiler |
| 03/01/1994 | US5291430 Method and apparatus for multiplying a plurality of numbers |
| 03/01/1994 | US5291076 Decoder/comparator and method of operation |
| 03/01/1994 | CA2013057C Plural dummy select chain logic synthesis network |
| 02/24/1994 | DE4227191A1 Digital electronic circuit for all four arithmetic operations - has adder circuit together with control circuit generating pulses for decimal point control and output generation |
| 02/23/1994 | EP0541683B1 Reduction processor |
| 02/22/1994 | US5289420 Method and circuit for transferring differential binary signals |
| 02/22/1994 | US5289400 Single-flux-quantum multiply-accumulator |
| 02/22/1994 | US5289399 Multiplier for processing multi-valued data |
| 02/22/1994 | US5289398 Small-sized low power consumption multiplication processing device with a rounding recording circuit for performing high speed iterative multiplication |
| 02/22/1994 | US5289397 High-speed modulo exponentiator device |
| 02/22/1994 | US5289396 Floating point processor with high speed rounding circuit |
| 02/22/1994 | US5289392 Adder |
| 02/22/1994 | US5289156 Data coupling arrangement |
| 02/22/1994 | CA2041657C Division method and apparatus including use of a z-z plot to select acceptable quotient bits |
| 02/16/1994 | EP0583120A1 Apparatus for controlling power delivery to selected portions of a multiplying device |
| 02/16/1994 | EP0582748A1 Divider device to divide a first polynomial by a second one |
| 02/16/1994 | CN1082284A Power-of-two length pseudo-noise sequence generator with fast offset adjustment |
| 02/15/1994 | US5287494 Sorting/merging tree for determining a next tournament champion in each cycle by simultaneously comparing records in a path of the previous tournament champion |
| 02/15/1994 | US5287434 Barcode identification system spooler |
| 02/15/1994 | US5287309 High-speed stack memory |
| 02/15/1994 | US5287299 Method and apparatus for implementing a digital filter employing coefficients expressed as sums of 2 to an integer power |
| 02/15/1994 | US5287296 Clock generators having programmable fractional frequency division |
| 02/09/1994 | EP0582083A1 A method and apparatus for generating pseudo-random numbers |
| 02/08/1994 | US5285406 High speed mixed radix adder |
| 02/08/1994 | US5285405 Inner product calculating circuit |
| 02/08/1994 | US5285404 Device for checking decimal data |
| 02/08/1994 | US5285403 Arithmetic processing module to be associated with a microprocessor central processing unit |
| 02/08/1994 | US5285271 Digital color matrixing circuit |
| 02/08/1994 | US5285185 Dual-coded data comparator |
| 02/03/1994 | WO1993024880A3 Low-power area-efficient absolute value arithmetic unit |
| 02/03/1994 | DE4219578A1 Electronic digital circuit for multiplication of coded numbers - has processing logic operated with gating signals from pulse generator based control circuit |
| 02/03/1994 | DE4218870A1 Electronic digital circuit for multiplication of coded numbers - has 4 bit adder circuit together with shift register operated by signals generated by control circuit |
| 02/03/1994 | DE4218089A1 Electronic digital circuit for addition and subtraction - has multiple modes provided by signals generated by control circuit |
| 02/03/1994 | DE4217286A1 Electronic digital circuit for addition and subtraction - has control circuit based around pulse generator unit to provide signals for various modes of operation |
| 02/03/1994 | DE4217048A1 Electronic digital circuit for subtraction and addition - has operating cycle modes controlled by circuit based upon pulse generator and logic devices |
| 02/03/1994 | DE4216375A1 Electronic digital circuit for addition and subtraction - has control circuit for improved reset control of multiple single or repeated additions and subtractions |
| 02/03/1994 | DE4216213A1 Electronic digital circuit for addition and subtraction - is operated in various modes using signals from control circuits with reduced number of components |
| 02/03/1994 | DE4212506A1 Digital multiplier circuit for coded numbers - has control circuit using single pulse generator coupled to logic coupled to flip=flops |
| 02/03/1994 | DE4211271A1 Electronic digital circuit for multiplication of coded numbers - uses 4 bit adder circuit operating with controller to provide built in facility for decimal point processing |
| 02/02/1994 | EP0580870A1 Multi-channel pseudo-random pattern generator |
| 02/01/1994 | US5283893 Method for sorting objects in a sequentially addressed array |