Patents
Patents for G06F 7 - Methods or arrangements for processing data by operating upon the order or content of the data handled (93,043)
03/1997
03/13/1997DE19532991A1 Multiplication procedure for two complex input magnitudes
03/12/1997EP0762692A2 Secure user certification for electronic commerce employing value metering system
03/12/1997EP0762268A1 Apparatus and method to determine a most significant digit
03/11/1997US5611021 Multiple pulse series generating device and method applicable to random pulse series generating apparatus
03/11/1997US5610850 Absolute difference accumulator circuit
03/11/1997US5610573 Method and apparatus for detecting assertion of multiple signals
03/11/1997US5610535 Programmable two-line, two-phase logic array
03/06/1997WO1997008870A2 Secure cryptographic methods for electronic transfer of information
03/06/1997WO1997008631A2 Signal processor with reduced complexity, and receiver comprising such a signal processor
03/06/1997WO1997008615A1 Seed rom for reciprocal computation
03/06/1997WO1997008614A1 Method and system for performing an l1 norm operation
03/06/1997WO1997008613A1 A galois field polynomial multiply/divide circuit and a digital signal processor incorporating same
03/06/1997WO1997008610A1 An apparatus for performing multiply-add operations on packed data
03/06/1997WO1997008609A1 Computer processor having a pipelined architecture and method of using same
03/06/1997WO1997008608A1 A set of instructions for operating on packed data
03/06/1997WO1997008607A1 Computer processor having a pipelined architecture which utilizes feedback and method of using same
03/06/1997WO1997008144A1 Substituted benzylaminopiperidine compounds
03/05/1997EP0760502A1 Ranking method for membership function values of linguistic input values in a fuzzy logic processor and device for carrying out the method
03/05/1997EP0760182A1 Method of error protected transmission, method of error protected reception of data and transmission system for transmission of data
03/05/1997EP0760119A1 Device for digitally carrying out a division operation
03/04/1997US5608887 Method of processing data strings
03/04/1997US5608801 Efficient cryptographic hash functions and methods for amplifying the security of hash functions and pseudo-random functions
03/04/1997US5608663 Computational array circuit for providing parallel multiplication
03/04/1997US5608662 Packet filter engine
02/1997
02/27/1997WO1997007451A2 Method and system for implementing data manipulation operations
02/26/1997EP0759198A1 Efficient median filter and method therefor
02/26/1997EP0340694B1 Test pattern generator
02/26/1997CN1143867A Pseudo random noise sequence code generator and CDMA radio communication terminal
02/26/1997CN1143860A Logic synthesizing method, semiconductor integrated circuit and operational circuit
02/25/1997US5606709 Register group circuit for data processing system
02/25/1997US5606677 Packed word pair multiply operation forming output including most significant bits of product and other bits of one input
02/25/1997US5606322 Divergent code generator and method
02/20/1997WO1997006600A1 Rational frequency divider and frequency synthesizer using the frequency divider
02/19/1997EP0758468A1 Digital frequency synthesizer
02/19/1997CN1143218A Method and device for determining number of leading zero or 1 in binary data threshold
02/18/1997US5604915 Data processing system having load dependent bus timing
02/18/1997US5604901 Interrogation index file comparison
02/18/1997US5604850 Method and system for dynamically generating computer instructions for performing a logical operation on bitmaps
02/18/1997US5604805 Privacy-protected transfer of electronic information
02/18/1997US5604691 Logarithm/inverse-logarithm converter utilizing a truncated Taylor series and method of use thereof
02/18/1997US5604689 Arithmetic logic unit with zero-result prediction
02/18/1997US5604429 Rectifying transfer gate circuit
02/13/1997WO1997005543A1 Log converter utilizing offset and method of use thereof
02/12/1997CA2183024A1 Method and apparatus for classifying raw data entries according to data patterns
02/11/1997US5603023 Processor circuit for heapsorting
02/11/1997US5603022 Data compression system and method representing records as differences between sorted domain ordinals representing field values
02/11/1997US5603012 Start code detector
02/11/1997US5602857 Error correction method and apparatus
02/11/1997US5602845 Method of generating a random element as well as a method for traffic mixing, random element generator and system component therewith
02/11/1997US5602769 Method and apparatus for partially supporting subnormal operands in floating point multiplication
02/11/1997US5602768 Method and apparatus for reducing the processing time required to solve square root problems
02/11/1997US5602767 Galois field polynomial multiply/divide circuit and a digital signal processor incorporating same
02/11/1997US5602766 Method of and device for forming the sum of a chain of products
02/11/1997US5602764 Comparing prioritizing memory for string searching in a data compression system
02/11/1997US5602545 Priority encoder
02/11/1997CA2055900C Binary tree multiplier constructed of carry save adders having an area efficient floor plan
02/06/1997WO1997004395A1 Method and apparatus for encryption key creation
02/06/1997WO1997004378A1 Microcircuit with memory that is protected by both hardware and software
02/06/1997WO1997004377A1 Single chip microprocessor, math co-processor, random number generator, real-time clock and ram having a one-wire interface
02/06/1997WO1997004376A1 Secure module with microprocessor and co-processor
02/05/1997EP0757312A1 Data processor
02/04/1997US5600847 Three input arithmetic logic unit with mask generator
02/04/1997US5600846 Data processing system and method thereof
02/04/1997US5600811 Vector move instruction in a vector data processing system and method therefor
02/04/1997US5600725 Digital signature method and key agreement method
02/04/1997US5600662 Error correction method and apparatus for headers
02/04/1997US5600584 Interactive formula compiler and range estimator
02/04/1997US5600583 Circuit and method for detecting if a sum of two multidigit numbers equals a third multidigit number prior to availability of the sum
02/04/1997US5600569 Method, system, and apparatus for automatically designing logic circuit, and multiplier
01/1997
01/29/1997EP0755537A1 Priority queue filtering system and method of operation
01/29/1997EP0598058B1 Method of imposing multi-object constraints on data files
01/28/1997US5598571 Data processor for conditionally modifying extension bits in response to data processing instruction execution
01/28/1997US5598362 Apparatus and method for performing both 24 bit and 16 bit arithmetic
01/28/1997US5598346 Array of configurable logic blocks including network means for broadcasting clock signals to different pluralities of logic blocks
01/22/1997EP0755121A2 Exponential and logarithmic conversion circuit
01/22/1997EP0755015A1 Combining data values
01/22/1997EP0754998A1 An arithmetic unit
01/22/1997EP0754997A2 Fetching apparatus for fetching data from a main memory
01/22/1997EP0754320A1 Circuit arrangement comprising a permutation unit and method of processing a batch of items
01/22/1997CN1140934A Apparatus and method of setting variable dividing radio and apparatus using the same
01/22/1997CN1140857A Information processing device equipped with a coprocessor which efficiently uses register data in main processor
01/21/1997US5596763 Three input arithmetic logic unit forming mixed arithmetic and boolean combinations
01/21/1997US5596746 Method for transforming relational data base schemas into object models using ideal table meta models
01/21/1997US5596733 System for exception recovery using a conditional substitution instruction which inserts a replacement result in the destination of the excepting instruction
01/21/1997US5596725 Fifo queue having replaceable entries
01/21/1997US5596617 Feedback shift register for generating digital signals representing series of pseudo-random numbers
01/21/1997US5596520 CMOS full adder circuit with pair of carry signal lines
01/21/1997US5596519 Iterative division apparatus, system and method employing left most one's detection and left most one's detection with exclusive OR
01/21/1997US5596518 Orthogonal transform processor
01/21/1997US5596516 Code sequence generator
01/15/1997EP0753172A1 Processing system and method of operation
01/15/1997EP0727066A4 Finite field inversion
01/15/1997CN1140497A Method and system for accumulating values in computing device
01/15/1997CN1140284A Sorting method, sort processing device and data processing apparatus
01/15/1997CN1140278A Computer processor utilizing logarithmic conversion and method of use thereof
01/14/1997US5594919 Method and system for reordering bytes in a data stream
01/14/1997US5594912 Digital signal processing device with optimized ALU circuit and logic block for controlling one of two registers based on the contents of the multiplication register
01/14/1997US5594656 Method of verification of a finite state sequential machine and resulting information support and verification tool
01/14/1997US5594366 Programmable logic device with regional and universal signal routing
01/09/1997WO1996038780A3 Method for performing signed division