| Patents for G06F 7 - Methods or arrangements for processing data by operating upon the order or content of the data handled (93,043) |
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| 06/15/1994 | EP0382839B1 Real time rank ordering logic circuit |
| 06/14/1994 | US5321752 Method of and apparatus for encryption and decryption of communication data |
| 06/14/1994 | US5321641 Pseudo random pattern generation circuit |
| 06/14/1994 | US5321640 Priority encoder and method of operation |
| 06/09/1994 | WO1994012928A1 Enhanced fast multiplier |
| 06/09/1994 | DE4240887A1 Electronic digital arithmetic circuit for addition, subtraction, multiplication and division - has four-bit adder and subtractor operating with shift registers and logic circuit for division and multiplication |
| 06/07/1994 | USRE34635 Method and apparatus for bit operational process |
| 06/07/1994 | US5319792 Modem having first and second registers enabling both to concurrently receive identical information in one context and disabling one to retain the information in a next context |
| 06/07/1994 | US5319789 Electromechanical apparatus having first and second registers enabling both to concurrently receive identical information in one context and disabling one to retain the information in a next context |
| 06/07/1994 | US5319788 Modified batcher network for sorting N unsorted input signals in log2 N sequential passes |
| 06/07/1994 | US5319764 Address detection circuit using a memory |
| 06/07/1994 | US5319763 Data processor with concurrent static and dynamic masking of operand information and method therefor |
| 06/07/1994 | US5319762 Associative memory capable of matching a variable indicator in one string of characters with a portion of another string |
| 06/07/1994 | US5319724 Apparatus and method for compressing still images |
| 06/07/1994 | US5319651 Data integrity features for a sort accelerator |
| 06/07/1994 | US5319588 Digital signal processor |
| 06/07/1994 | US5319347 Parallelized magnitude comparator for comparing a binary number to a fixed value |
| 06/01/1994 | DE4241129A1 Digital electronic arithmetic circuit for all four operations - performs addition and subtraction in negative number range and also in transition range |
| 06/01/1994 | DE4239964A1 Calculating circuit for adding, subtraction, multiplication and division - adds and subtracts in negative number range, and also in transition range |
| 05/31/1994 | US5317756 Data processor for detecting identical data coexisting in a plurality of data section of data transmission paths |
| 05/31/1994 | US5317753 Coordinate rotation digital computer processor (cordic processor) for vector rotations in carry-save architecture |
| 05/31/1994 | US5317531 Apparatus for reducing the size of an arithmetic and logic unit necessary to practice non-restore division |
| 05/31/1994 | US5317530 Rounding operation circuit |
| 05/31/1994 | US5317528 Random number generator |
| 05/31/1994 | US5317527 Leading one/zero bit detector for floating point operation |
| 05/31/1994 | US5317526 Format conversion method of floating point number and device employing the same |
| 05/31/1994 | US5317204 Mitigating the adverse effects of charge sharing in dynamic logic circuits |
| 05/26/1994 | WO1994011849A1 Mobile telephone systems and a method for carrying out financial transactions by means of a mobile telephone system |
| 05/25/1994 | EP0598347A2 Two stage accumulator for use in updating coefficients |
| 05/25/1994 | EP0598112A1 Process and configuration for establishing the sum of a chain of products |
| 05/25/1994 | EP0598058A1 Method of imposing multi-object constraints on data files. |
| 05/24/1994 | US5315599 Microprocessor-based monitoring or protection device comprising an analog data acquisition system |
| 05/24/1994 | US5315540 Method and hardware for dividing binary signal by non-binary integer number |
| 05/24/1994 | CA2007059C Register and arithmetic logic unit |
| 05/24/1994 | CA2007054C Multiplier |
| 05/18/1994 | EP0597083A1 Shift and add digital signal processor |
| 05/18/1994 | EP0584265A4 Null convention speed independent logic |
| 05/18/1994 | EP0541678B1 An arithmetic unit for structure arithmetic |
| 05/18/1994 | EP0497777B1 Methods of realizing digital signal processors using a programmed compiler |
| 05/17/1994 | US5313648 Signal processing apparatus having first and second registers enabling both to concurrently receive identical information in one context and disabling one to retain the information in a next context |
| 05/17/1994 | US5313576 Graphics system |
| 05/17/1994 | US5313530 Calculating apparatus and method of encrypting/decrypting communication data by using the same |
| 05/17/1994 | US5313509 Pulse counter with arbitrary output characteristic |
| 05/17/1994 | US5313474 Method and apparatus to determine the log of an element in GF(2m) with the help of a small adjustable size table |
| 05/17/1994 | US5313415 Method and apparatus for performing floating point arithmetic operation and rounding the result thereof |
| 05/17/1994 | US5313414 Canonical signed two's complement constant multiplier compiler |
| 05/17/1994 | US5313231 Color palette device having big/little endian interfacing, systems and methods |
| 05/11/1994 | EP0596691A2 Multi-function resonant tunneling logic gate and method of performing binary and multi-valued logic |
| 05/11/1994 | EP0596175A1 Apparatus for executing the argument reduction in exponential computations of IEEE standard floating-point numbers |
| 05/11/1994 | EP0596080A1 Digital sensor signal numerical differentiation process |
| 05/11/1994 | DE4238695A1 Electronic calculator circuit for all four arithmetic operations - uses limited reset function when previous result is used in subsequent operation, with first pulse circuit resetting second pulse circuit, and second pulse circuit resetting first |
| 05/11/1994 | DE4237758A1 Digital electronic circuit for addition, subtraction, multiplication and addition - has four-bit switched tetrade circuit, and limited reset with certain shift registers which are non reset-triggered |
| 05/10/1994 | US5311519 Multiplexer |
| 05/10/1994 | US5311460 Method and apparatus for performing high speed divide operations |
| 05/10/1994 | US5311458 CPU with integrated multiply/accumulate unit |
| 05/05/1994 | DE4236615A1 Digital electronic circuit for addition, subtraction, division and multiplication - has four bit numbers fed to switchable binary adder and subtractor operating with shift registers and control pulse generator, with main circuit formed so that conductor path is clearly recognisable |
| 05/05/1994 | DE4236606A1 Electronic calculator for addition and subtraction in cash register - closely arranges sub-circuits of shift register and storage rows |
| 05/04/1994 | EP0595224A1 Method and apparatus for early quotient completion in arithmetic division |
| 05/04/1994 | EP0594969A1 Data processing system and method for calculating the sum of a base plus offset |
| 05/04/1994 | EP0493466B1 Word width reduction system for videosignal processing and transmission |
| 05/03/1994 | US5309494 Circuit configuration for generating logical butterfly structures |
| 05/03/1994 | US5309384 Digital multiplier with carry-sum input |
| 05/03/1994 | US5309383 Floating-point division circuit |
| 05/03/1994 | CA2002264C Information processing device capable of indicating performance |
| 04/28/1994 | WO1994009443A1 Non-numeric coprocessor |
| 04/28/1994 | CA2146352A1 Non-numeric coprocessor |
| 04/27/1994 | EP0594241A1 Arrangement for storing an information signal in a memory and retrieving the information signal from said memory |
| 04/27/1994 | EP0593713A1 Exponential/logarithmic computational apparatus and method |
| 04/26/1994 | US5307485 Method and apparatus for merging sorted lists in a multiprocessor shared memory system |
| 04/26/1994 | US5307375 Two stage accumulator for use in updating coefficients |
| 04/26/1994 | US5307303 Method and apparatus for performing division using a rectangular aspect ratio multiplier |
| 04/26/1994 | US5307302 Square root operation device |
| 04/26/1994 | US5307301 Floating point safe instruction recognition method |
| 04/26/1994 | US5307300 High speed processing unit |
| 04/26/1994 | US5307061 Absolute value circuit |
| 04/26/1994 | CA2084885C Device and method for evaluating trigonometric functions |
| 04/26/1994 | CA2045662C Binary floating point arithmetic rounding in conformance with ieee 754-1985 standard |
| 04/26/1994 | CA1328742C Electronic combination lock with changeable entry codes, lock-out codes and programming code |
| 04/21/1994 | DE4234975A1 Digital electronic circuit for addition, subtraction multiplication and division - has circuit based brown binary adder and shift registers together with pulse generator units |
| 04/20/1994 | EP0593107A1 Data processing system |
| 04/20/1994 | EP0593073A1 A processor incorporating shifters |
| 04/19/1994 | US5305463 Null convention logic system |
| 04/19/1994 | US5305432 Line segment depicting system for a display image memory |
| 04/19/1994 | US5305399 Two dimensional shift-array for use in image compression VLSI |
| 04/19/1994 | US5305249 Digital signal processor for video signals |
| 04/19/1994 | US5305248 Fast IEEE double precision reciprocals and square roots |
| 04/19/1994 | US5305247 Method and processor for high-speed convergence factor determination |
| 04/19/1994 | US5304994 Minimal delay leading one detector with result bias control |
| 04/15/1994 | CA2086786A1 Trainable automated imaging device |
| 04/14/1994 | DE4234141A1 Digital circuit for addition and subtraction e.g. for cash till - has arrays of flip=flip stages providing inputs to processing circuit, with numbers input from right to left so that digits with value one are keyed in first |
| 04/14/1994 | DE4234134A1 Digital electronic circuit for addition and subtraction - provides diodes at connections of long cross lines where OR=gates are normally located |
| 04/13/1994 | EP0591846A2 Subtracting method and device in or relating to signal processing technologies |
| 04/13/1994 | EP0591593A1 Device and method of managing asynchronous events in a finite state machine |
| 04/13/1994 | EP0591562A1 Programm controlled optimization of a processor controlled circuit for producing an algorithmically generatable data output sequence |
| 04/13/1994 | EP0591490A1 Implementation techniques of self-checking arithmetic operators and data paths based on double-rail and parity codes |
| 04/12/1994 | US5303381 Method and apparatus for sorting sequential input signals by concurrently comparing successive input signals among signals in first and second memory sections |
| 04/12/1994 | US5303376 Program partial linking system for linking a specific program prepared in advance when an assigned program is not in a program library |
| 04/12/1994 | US5303354 Data transfer system between registers for microcomputer |
| 04/12/1994 | US5303178 Multiplying system based on the Booth's algorithm and generating a positive or negative product in response to a mode signal |
| 04/12/1994 | US5303177 Method and device for performing an approximate arithmetical division |