| Patents for G06F 7 - Methods or arrangements for processing data by operating upon the order or content of the data handled (93,043) |
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| 06/29/1995 | DE4434895A1 Verfahren und Vorrichtung zur Erholung von Ablaufunterbrechungen in einem Computersystem Process and apparatus for recovery of flow interruptions in a computer system |
| 06/29/1995 | CA2178919A1 Parallel processing of digital signals in a single arithmetic/logic unit |
| 06/28/1995 | EP0660246A2 Signal processor |
| 06/28/1995 | EP0660229A1 Method and apparatus for modifying the contents of a register |
| 06/28/1995 | EP0660227A2 Three input arithmetic logic unit forming the sum of a first and a second boolean combination of the inputs |
| 06/28/1995 | EP0660226A2 Limiter circuit |
| 06/28/1995 | EP0660225A1 ALU capable of simultaneously executing a plurality of operations |
| 06/27/1995 | US5428561 Efficient pseudorandom value generator |
| 06/22/1995 | WO1995016951A1 Method and apparatus for integer division |
| 06/21/1995 | EP0658256A1 High performance mantissa divider |
| 06/20/1995 | US5426785 Comparator stack architecture for order statistic filtering of digital imagery |
| 06/20/1995 | US5426743 Computing apparatus |
| 06/20/1995 | US5426682 Sequential logic circuit having state hold circuits |
| 06/20/1995 | US5426600 Double precision division circuit and method for digital signal processor |
| 06/20/1995 | US5426599 Hardware implemented multiplier for performing multiplication of two digital data according to booth algorithm |
| 06/20/1995 | US5426598 Adder and multiplier circuit employing the same |
| 06/15/1995 | WO1995016234A1 Apparatus and method for signal processing |
| 06/14/1995 | EP0657805A1 Result normalizer and method of operation |
| 06/14/1995 | EP0657804A1 Overflow control for arithmetic operations |
| 06/14/1995 | EP0657803A2 Three input arithmetic logic unit forming the sum of a first input added with a first boolean combination of a second input and third input plus a second boolean combination of the second and third inputs |
| 06/14/1995 | EP0578692B1 Position-sensing apparatus |
| 06/14/1995 | EP0337985B1 Computational method and apparatus for finite field multiplication |
| 06/14/1995 | DE4430195A1 Computersystem und Verfahren zur Auswertung von Vorhersagen und Booleschen Ausdrücken Computer system and method for evaluation of predictions and Boolean expressions |
| 06/13/1995 | US5424981 Memory device |
| 06/13/1995 | US5424972 Carry look ahead circuit |
| 06/13/1995 | US5424971 Unsigned constant multiplier compiler |
| 06/13/1995 | US5424970 Method and apparatus for multiplying a plurality of N numbers |
| 06/13/1995 | US5424969 Product-sum operation unit |
| 06/13/1995 | US5424968 Priority encoder and floating-point adder-substractor |
| 06/13/1995 | US5424967 Shift and rounding circuit and method |
| 06/13/1995 | US5424734 Variable logic operation apparatus |
| 06/08/1995 | WO1995015633A1 A non-deterministic public key encryption system |
| 06/07/1995 | EP0656709A2 Encryption device and apparatus for encryption/decryption based on the Montgomery method using efficient modular multiplication |
| 06/07/1995 | EP0656583A1 Series parallel converter including pseudorandom noise generation |
| 06/07/1995 | EP0656582A1 Parallel adding and averaging circuit and method |
| 06/06/1995 | US5423052 Central processing unit with switchable carry and borrow flag |
| 06/06/1995 | US5423015 Memory structure and method for shuffling a stack of data utilizing buffer memory locations |
| 06/06/1995 | US5423010 Structure and method for packing and unpacking a stream of N-bit data to and from a stream of N-bit data words |
| 06/06/1995 | US5422979 Fuzzy logic controller with optimized storage organization |
| 06/06/1995 | US5422923 Programmable time-interval generator |
| 06/06/1995 | US5422835 Digital clock signal multiplier circuit |
| 06/06/1995 | US5422823 Programmable gate array device having cascaded means for function definition |
| 06/06/1995 | US5422805 Method and apparatus for multiplying two numbers using signed arithmetic |
| 06/01/1995 | DE4422208A1 Verfahren und Vorrichtung zum stabilen Partitionieren einer sequentiellen Liste in einer Raum-adaptiven Weise Method and apparatus for stable partitioning a sequential list in a space-adaptive manner |
| 05/31/1995 | EP0655685A1 Parity bit calculation device associated with a sum of two numbers |
| 05/31/1995 | EP0655683A1 Circuit architecture and corresponding method for testing a programmable logic matrix |
| 05/31/1995 | EP0655680A1 Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section |
| 05/31/1995 | EP0655677A1 Parallel shift and add circuit and method |
| 05/31/1995 | EP0655676A2 Three input arithmetic logic unit forming mixed arithmetic and boolean combinations |
| 05/31/1995 | EP0655675A1 Shift and rounding circuit and method |
| 05/30/1995 | US5421010 Circuit and a method for selecting the kappa greatest data in a data sequence |
| 05/30/1995 | US5421007 Key space analysis method for improved record sorting and file merging |
| 05/30/1995 | US5420928 Pseudo-random generator |
| 05/30/1995 | US5420925 Rolling code encryption process for remote keyless entry system |
| 05/30/1995 | US5420815 Digital multiplication and accumulation system |
| 05/24/1995 | EP0654733A1 Parallel data processing in a single processor |
| 05/24/1995 | EP0654732A1 Galois field multiplication method and multiplier utilizing the same |
| 05/24/1995 | EP0654731A1 Multiplier with a layout capable of repeating multiplications without the use of an external bus |
| 05/24/1995 | DE4438652A1 Verfahren und Vorrichtung zum stabilen Sortieren oder Mischen sequentieller Listen in einer raumadaptiven Weise Method and apparatus for stable sorting or merging sequential lists in a space-adaptive manner |
| 05/23/1995 | US5418976 Processing system having a storage set with data designating operation state from operation states in instruction memory set with application specific block |
| 05/23/1995 | US5418736 Optimized binary adders and comparators for inputs having different widths |
| 05/17/1995 | EP0653716A1 Method of verification of a finite state sequential machine and resulting information support and verification tool |
| 05/17/1995 | EP0653702A1 Carry chain adder using regenerative push-pull differential logic |
| 05/16/1995 | US5416733 Apparatus for finding quotient in a digital system |
| 05/11/1995 | WO1995012845A1 Finite field inversion |
| 05/10/1995 | EP0652507A1 Binary number squaring circuit |
| 05/10/1995 | EP0449994B1 A distributed parallel processing network wherein the connection weights are generated using stiff differential equations |
| 05/09/1995 | US5414865 Self-programming with limited sequential memory capacity |
| 05/09/1995 | US5414842 External sorting using virtual storage as a work device |
| 05/09/1995 | US5414830 Apparatus for serialization and deserialization of data, and resultant system for digital transmission of serial data |
| 05/09/1995 | US5414721 Serial data receiving device |
| 05/09/1995 | US5414719 Operating circuit for galois field |
| 05/09/1995 | US5414651 Arithmetic unit for multiplying long integers modulo M and R.S.A. converter provided with such multiplication device |
| 05/04/1995 | DE4336655A1 Schaltungsanordnung zur Frequenzmultiplikation Circuit arrangement for frequency multiplication |
| 05/03/1995 | EP0651514A2 Programmable dedicated FPGA functional blocks for multiple wide-input functions |
| 05/03/1995 | EP0651304A2 Constructing method of finite-state machine performing transitions according to a partial type of success funtion and a failure function |
| 05/02/1995 | US5412795 State machine having a variable timing mechanism for varying the duration of logical output states of the state machine based on variation in the clock frequency |
| 05/02/1995 | US5412665 Parallel operation linear feedback shift register |
| 05/02/1995 | US5412591 Schematic compiler for a multi-format high speed multiplier |
| 05/02/1995 | US5412588 Digital sine-wave generating circuit |
| 05/02/1995 | US5412587 Pseudorandom stochastic data processing |
| 05/02/1995 | US5412368 Digital signal comparison circuitry |
| 05/02/1995 | CA2046320C Method and device for generating random numbers in a system comprising portable electronic objects |
| 04/27/1995 | DE4342639C1 Full adding stage and use |
| 04/27/1995 | DE4335925A1 Circuit arrangement for signal processing in accordance with the CORDIC method |
| 04/26/1995 | EP0650115A1 Multiplier capable of calculating double precision, single precision, inner product and multiplying complex numbers |
| 04/26/1995 | EP0649558A1 Transmission system comprising at least a coder |
| 04/26/1995 | EP0649557A1 Transmission system comprising at least a coder |
| 04/25/1995 | US5410727 Input/output system for a massively parallel, single instruction, multiple data (SIMD) computer providing for the simultaneous transfer of data between a host computer input/output system and all SIMD memory devices |
| 04/25/1995 | US5410722 Queue system for dynamically allocating and moving memory registers between a plurality of pseudo queues |
| 04/25/1995 | US5410719 Field compositor for merging data and including cells each receiving three control and two data inputs and generating one control and one data output therefrom |
| 04/25/1995 | US5410689 System for merge sorting that assigns an optical memory capacity to concurrent sort cells |
| 04/25/1995 | US5410677 Apparatus for translating data formats starting at an arbitrary byte position |
| 04/25/1995 | US5410657 Method and system for high speed floating point exception enabled operation in a multiscalar processor system |
| 04/25/1995 | US5410582 Reference-signal generating apparatus |
| 04/25/1995 | CA2046289C Method for generating random numbers in a data processing system and system using said method |
| 04/20/1995 | WO1995010803A1 Processor for variable-length character strings |
| 04/18/1995 | US5408670 Performing arithmetic in parallel on composite operands with packed multi-bit components |
| 04/18/1995 | US5408657 Method of imposing multi-object constraints on data files in a data processing system |
| 04/18/1995 | US5408654 Method to reorganize an index file without sorting by changing the physical order of pages to match the logical order determined from the index structure |