Patents
Patents for G06F 7 - Methods or arrangements for processing data by operating upon the order or content of the data handled (93,043)
04/1998
04/07/1998US5737252 Circuit arrangement comprising a permutation unit and method of processing a batch of items
04/07/1998US5737251 Rank order filter
04/07/1998US5736893 Digital method and apparatus for reducing EMI emissions in digitally-clocked systems
04/01/1998EP0833259A2 Method and apparatus for coupling object state and behavior in a database management system
04/01/1998EP0833245A1 Circuit with combinatorial logic blocks located between registers
04/01/1998EP0833244A1 Arithmetic cell for field programmable devices
03/1998
03/31/1998US5734879 Saturation instruction in a data processor
03/31/1998US5734601 Booth multiplier with low power, high performance input circuitry
03/31/1998US5734600 Polynomial multiplier apparatus and method
03/31/1998US5734599 Performing a population count using multiplication
03/31/1998US5734584 Integrated structure layout and layout of interconnections for an integrated circuit chip
03/26/1998WO1998012629A1 Digital signal processing integrated circuit architecture
03/26/1998WO1998012627A1 Input operand control in data processing systems
03/26/1998WO1998012624A1 Data processing apparatus registers
03/25/1998EP0831396A2 Sticky bit determination in floating point arithmetic system
03/25/1998EP0830783A1 Method and apparatus for copy protection for various recording media using a video finger print
03/25/1998EP0830742A1 Improved system for correction of three and four errors
03/24/1998US5732138 Method for seeding a pseudo-random number generator with a cryptographic hash of a digitization of a chaotic system
03/24/1998US5732008 Low-power high performance adder
03/24/1998US5732005 Single-precision, floating-point register array for floating-point units performing double-precision operations by emulation
03/19/1998WO1998011481A1 Fast n-bit by n-bit multipliers using 4-bit by 4-bit multipliers and cascaded adders
03/19/1998DE19735870A1 Interrupt and exception handling in asymmetric multiprocessor architecture for multimedia
03/18/1998EP0829803A2 Digital signal processor and method for performing a multiplication in a digital signal processor
03/18/1998CN1176714A Improved system for correction of three and four errors
03/18/1998CN1176699A LNS-based computer processor and method of use thereof
03/18/1998CN1176437A System and method for handling interrupt and exception events in asymmetric multiprocessor architecture
03/18/1998CN1176425A Arithmetic processing device
03/17/1998US5729759 Data processing apparatus for performing cumulative processing on time series data
03/17/1998US5729732 System and method for sorting data in a computer system using edge buckets for key values having a maximum and minimum range within a subinterval
03/17/1998US5729725 Mask data generator and bit field operation circuit
03/17/1998US5729487 Electronic component capable, in particular, of performing a division of two numbers to the base 4.
03/17/1998US5729486 Digital dividing apparatus using a look-up table
03/17/1998US5729485 Fast determination of carry inputs from lower order product for radix-8 odd/even multiplier array
03/17/1998US5729482 Microprocessor shifter using rotation and masking operations
03/17/1998US5729481 Method and system of rounding for quadratically converging division or square root
03/17/1998US5729190 Dynamic comparator circuit for cache memories
03/12/1998WO1998010354A1 Information processing circuit, microcomputer and electronic apparatus
03/12/1998WO1998010342A2 Anti-virus agent for use with databases and mail servers
03/12/1998DE19724270A1 Register data file
03/11/1998EP0828349A1 Method of and apparatus for generating random numbers
03/11/1998EP0787325A4 Error correction method and apparatus for disk drive emulator
03/11/1998EP0704075A4 Method and apparatus for indexing searching and displaying data
03/11/1998CN1175730A Method and apparatus for performing microprocessor integer division operations using floating point hardware
03/10/1998US5727200 Parallel merge sorting apparatus with an accelerated section
03/10/1998US5727063 Pseudo-random generator
03/10/1998US5726942 Hierarchical encoder including timing and data detection devices for a content addressable memory
03/10/1998US5726928 Arithmetic logic unit circuit with reduced propagation delays
03/10/1998US5726927 Multiply pipe round adder
03/10/1998US5726926 Shifter for shifting floating point number utilizing arithmetic operation of redundant binary number, and adder containing the same
03/10/1998US5726924 Exponentiation circuit utilizing shift means and method of using same
03/10/1998US5726923 Minimum/maximum data detector
03/10/1998US5726658 CDMA code generator employing mixing ergodic transformation
03/05/1998WO1998009379A1 Frequency dividing circuit
03/04/1998EP0827087A2 Computation apparatus and method
03/04/1998EP0827069A2 Arithmetic circuit and method
03/04/1998EP0827068A2 Floating point number data processing means
03/04/1998CN1175030A Column address counter with 2 subtracter used for address compare
03/03/1998US5724572 Method and apparatus for processing null terminated character strings
03/03/1998US5724280 Accelerated booth multiplier using interleaved operand loading
03/03/1998US5724279 In an electronic system
03/03/1998US5724276 Logic block structure optimized for sum generation
03/03/1998US5724275 Fast multi-operand bit pattern detection method and circuit
03/03/1998CA2110145C Methods and apparatus for correcting customer address lists
02/1998
02/25/1998EP0825523A1 Method and circuit for multiplying a multiplicand and a multiplier by the Booth-method in iterative steps
02/24/1998US5721941 Character processing apparatus and method involving a tab
02/24/1998US5721892 Processor
02/24/1998US5721809 Maximum value selector
02/24/1998US5721697 Performing tree additions via multiplication
02/24/1998CA2072526C Digital sigma-delta modulator and arithmetic overflow protected adder
02/19/1998WO1998007253A1 Accelerating public-key cryptography by precomputing randomly generated pairs
02/19/1998WO1998007251A1 Improved cryptographically secure pseudo-random bit generator for fast and secure encryption
02/18/1998CN1173931A Method and appts. for custom operations of a processor
02/18/1998CN1173930A Logarithm/inverse-logarithm converter utilizing second-order term and method of using same
02/17/1998US5720002 Neural network and method of using same
02/17/1998US5719940 Method for providing information security by exchanging authentication and signing an electronic signature and apparatus therefor
02/17/1998US5719913 Pseudo-random number generating circuit and bidirectional shift register
02/17/1998US5719809 Memory device
02/17/1998US5719803 High speed addition using Ling's equations and dynamic CMOS logic
02/17/1998US5719802 Adder circuit incorporating byte boundaries
02/17/1998US5719798 Programmable modulo k counter
02/12/1998WO1998006175A1 Method of and apparatus for generating random numbers
02/12/1998WO1998006034A1 Low-level endian-independent machine language program representation
02/12/1998WO1998006031A1 Floating point addition methods and apparatus
02/12/1998WO1998006030A1 Multifunctional execution unit
02/12/1998WO1998006029A1 Apparatus and methods for execution of computer instructions
02/11/1998EP0823104A1 Electronic credit card and process for reloading an electronic credit card
02/11/1998EP0823083A1 System for performing arithmetic operations with single or double precision
02/11/1998CN1172985A Electronic apparatus
02/10/1998US5717947 Data processing system and method thereof
02/10/1998US5717944 Autonomous SIMD/MIMD processor memory elements
02/10/1998US5717943 Computer system
02/10/1998US5717928 System and a method for obtaining a mask programmable device using a logic description and a field programmable device implementing the logic description
02/10/1998US5717915 Method of merging large databases in parallel
02/10/1998US5717899 System for writing words into memory in first order and concurrently reading words from memory in second order based on input output ranks of words
02/10/1998US5717698 Method and apparatus for testing a network with a programmable logic matrix
02/10/1998US5717622 Selecting circuit including circuits having different time constants to which each of a plurality of input signals is applied, and adding circuit using the same
02/10/1998US5717616 Computer hardware instruction and method for computing population counts
02/05/1998WO1998004973A1 Data de-rotator and de-interleaver
02/04/1998EP0822481A1 Constant divider
02/04/1998CN1172539A Logarithm/inverse-logarithm converter utilizing truncated taylor series and method of use thereof