Patents
Patents for G06F 7 - Methods or arrangements for processing data by operating upon the order or content of the data handled (93,043)
11/1997
11/19/1997EP0807287A1 Logarithm/inverse-logarithm converter utilizing a truncated taylor series and method of use thereof
11/19/1997EP0807285A1 Logarithm/inverse-logarithm converter utilizing second-order term and method of using same
11/19/1997CN1165436A 随机码发生器 Random code generator
11/18/1997US5689721 Detecting overflow conditions for negative quotients in nonrestoring two's complement division
11/18/1997US5689693 Range finding circuit for selecting a consecutive sequence of reorder buffer entries using circular carry lookahead
11/18/1997US5689592 Parallel processing of digital signals in a single arithmetic/logic unit
11/18/1997US5689452 Method and apparatus for performing arithmetic in large galois field GF(2n)
11/18/1997US5689451 Device for calculating parity bits associated with a sum of two numbers
11/18/1997US5689450 For processing of an input signal
11/18/1997US5689228 Parallel magnitude comparison using manchester carry chains
11/13/1997WO1997042706A1 Circuit arrangement for generating random bit sequences
11/13/1997DE19714756A1 Data processing circuit structure for describing or modelling of digital circuit
11/12/1997EP0806722A1 Method and apparatus for a multiply and accumulate circuit having a dynamic saturation range
11/12/1997EP0806007A1 A parametrizable control module comprising first and second loadables counters, an electronic circuit comprising a plurality of such parametrized control modules, and a method for synthesizing such circuit
11/12/1997EP0699318A4 Unified floating point and integer datapath for risc processor
11/11/1997US5687340 Reduced area floating point processor control logic utilizing a decoder between a control unit and the FPU
11/11/1997US5687252 Image processing apparatus
11/11/1997US5687107 Exclusive-OR gate, an inverted type selector, and adders
11/11/1997US5687106 Implementation of binary floating point using hexadecimal floating point unit
11/05/1997EP0804758A1 Elliptic curve encryption systems
11/05/1997EP0676081A4 Pattern search and refresh logic in dynamic memory.
11/04/1997US5685008 Computer Processor utilizing logarithmic conversion and method of use thereof
11/04/1997US5684985 Method and apparatus utilizing bond identifiers executed upon accessing of an endo-dynamic information node (EDIN)
11/04/1997US5684849 Digital circuit for detecting coincidence of two successive words of incoming serial data and a method thereof
11/04/1997US5684731 Booth multiplier using data path width adder for efficient carry save addition
11/04/1997US5684730 Booth multiplier for trigonometric functions
11/04/1997US5684729 Floating-point addition/substraction processing apparatus and method thereof
11/04/1997US5684728 Data processing system having a saturation arithmetic operation function
11/04/1997US5684435 Analog waveform communications reduced instruction set processor
10/1997
10/29/1997EP0803800A2 A sort processor and a sort processing device
10/29/1997CN1163544A Switching system with renewing number dictionary decoding data processor
10/28/1997US5682545 Microcomputer having 16 bit fixed length instruction format
10/28/1997US5682405 Ones density monitor
10/28/1997US5682342 High-speed counter
10/28/1997US5682340 Low power consumption circuit and method of operation for implementing shifts and bit reversals
10/28/1997US5682054 Rectifying transfer gate device
10/23/1997WO1997039404A1 An execute unit configured to selectably interpret an operand as multiple operands or as a single operand
10/23/1997DE19632246C1 Multiplication system using modified Booth algorithm
10/22/1997EP0801847A1 Null convention threshold gate
10/22/1997EP0669031B1 Method for carrying out financial transactions by means of a mobile telephone system
10/22/1997CN1163007A 数字运算电路 Digital arithmetic circuit
10/22/1997CN1163002A Process for designing a fuzzy-controller
10/21/1997US5680516 Multiple pulse series generating device and method applicable to random pulse series generating apparatus
10/21/1997US5680339 Method for rounding using redundant coded multiply result
10/16/1997WO1997038371A1 Communication system with a master station and at least one slave station
10/16/1997DE19630435C1 Multiplication circuit for complex values
10/16/1997CA2640992A1 Digital signatures on a smartcard
10/15/1997EP0801345A1 Circuit and method for modulo multiplication and exponentiation arithmetic
10/15/1997CN1162229A Difference detection receiver
10/15/1997CN1162153A Device for executing self-timing algorithm and method thereof
10/14/1997US5678055 Method and device for generating Grobner bases to reduce memory usage and increase computing speed
10/14/1997US5678043 Data compression and encryption system and method representing records as differences between sorted domain ordinals that represent field values
10/14/1997US5677995 Method and apparatus for implementing TDM fuzzy control
10/14/1997US5677863 Method of performing operand increment in a booth recoded multiply array
10/14/1997US5677862 Method for multiplying packed data
10/14/1997US5677861 Arithmetic apparatus for floating-point numbers
10/14/1997US5677860 Overflow and underflow processing circuit of a binary adder
10/09/1997WO1997037299A1 Fractional precision integer square root processor and method for use with electronic circuit breaker systems
10/08/1997EP0800276A1 A frequency multiplying circuit having a first stage with greater multiplying ratio than subsequent stages
10/08/1997EP0394499B1 Apparatus for multiplication, division and extraction of square root
10/08/1997CN1161726A Electronic security system
10/08/1997CN1161499A Device and method for processing letters and marks information
10/07/1997US5675822 Method and apparatus for a digital signal processor having a multiplierless computation block
10/07/1997US5675808 Power control of circuit modules within an integrated circuit
10/07/1997US5675528 Early detection of overflow and exceptional quotient/remainder pairs for nonrestoring twos complement division
10/07/1997US5675527 Multiplication device and sum of products calculation device
10/07/1997US5675526 Processor performing packed data multiplication
10/07/1997CA2070035C Arrangement and method of ascertaining data word number of maximum or minimum in a plurality of data words
10/02/1997WO1997036227A2 Method and computer system for processing a set of data elements on a sequential processor
10/01/1997EP0798723A2 Information recording medium apparatus for recording the same and apparatus for reproducing the same
10/01/1997EP0797806A1 Method and apparatus for binary-oriented set sequencing
09/1997
09/30/1997US5673397 FIFO queue having replaceable entries
09/30/1997US5673321 Efficient selection and mixing of multiple sub-word items packed into two or more computer words
09/30/1997US5673216 Process and system for adding or subtracting symbols in any base without converting to a common base
09/30/1997US5673215 Non-restoring fixed-point divider apparatus
09/30/1997CA2018271C Digital arrangement for error checking in binary adder including block carry look-ahead units
09/24/1997CN1160467A Method and apparatus for inserting source identificationd data into video signal
09/23/1997US5671446 Method and apparatus for atomically accessing a queue in a memory structure where LIFO is converted to FIFO
09/23/1997US5671432 Programmable array I/O-routing resource
09/23/1997US5671406 Data structure enhancements for in-place sorting of a singly linked list
09/23/1997US5671405 Apparatus and method for adaptive logical partitioning of workfile disks for multiple concurrent mergesorts
09/23/1997US5671228 System for detecting non-coincidence of codes
09/23/1997US5671171 Shared rounding hardware for multiplier and divider/square root unit using conditional sum adder
09/23/1997US5671170 Method and apparatus for correctly rounding results of division and square root computations
09/23/1997US5671166 Barrel shifter for combining pieces of data into a piece of combined data and shifting the combined data
09/23/1997US5671151 Self-timed logic circuit having zero-latency overhead and method for designing same
09/23/1997US5670900 Mask decoder circuit optimized for data path
09/23/1997CA2078704C Absolute value circuit
09/18/1997WO1997034223A1 Logic elements for interlaced carry/borrow systems having a uniform layout
09/17/1997EP0795819A1 Method and apparatus for the processing of digital signals in one-hot RNS
09/17/1997EP0795818A1 Multiplier with variable resolution for a signal processor
09/17/1997EP0795161A2 Signal processor with reduced complexity, and receiver comprising such a signal processor
09/17/1997EP0795155A1 A microprocessor having a multiply operation
09/17/1997EP0795154A1 Microprocessor with compare operation of composite operands
09/17/1997EP0744054A4 High speed function generating apparatus and method
09/16/1997US5669012 Data processor and control circuit for inserting/extracting data to/from an optional byte position of a register
09/16/1997US5668989 Two-digit hybrid radix year numbers for year 2000 and beyond
09/16/1997US5668976 Error correction method and apparatus for disk drive emulator
09/16/1997US5668878 Secure cryptographic methods for electronic transfer of information
09/16/1997US5668603 Video finger print method and apparatus