| Patents for G06F 7 - Methods or arrangements for processing data by operating upon the order or content of the data handled (93,043) |
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| 07/10/1997 | CA2213293A1 Improved system for correction of three and four errors |
| 07/09/1997 | EP0782727A1 Digital arithmetic circuit |
| 07/09/1997 | EP0782725A1 Computer with two-dimensional merge tournament sort using caching |
| 07/09/1997 | CN1153947A High-speed multiplier to multiply digital signal by periodic signal |
| 07/08/1997 | US5646967 Multi-phase triangular wave synthesizer for phase-to-frequency converter |
| 07/08/1997 | US5646877 High radix multiplier architecture |
| 07/08/1997 | US5646876 Method and apparatus for reducing rounding error when evaluating binary floating point polynomials |
| 07/08/1997 | US5646875 Denormalization system and method of operation |
| 07/08/1997 | US5646874 Multiplication/multiplication-accumulation method and computing device |
| 07/08/1997 | US5646873 Barrel shifter device and variable-length decoder |
| 07/08/1997 | US5646621 Delta-sigma ADC with multi-stage decimation filter and gain compensation filter |
| 07/08/1997 | US5646555 Pipeline structure using positive edge and negative edge flip-flops to decrease the size of a logic block |
| 07/03/1997 | WO1997023822A1 A system for providing the absolute difference of unsigned values |
| 07/03/1997 | WO1997023821A1 A system for signal processing using multiply-add operations |
| 07/02/1997 | EP0782319A2 Apparatus for symmetrically reducing "N" least significant bits of an M-Bit digital signal |
| 07/02/1997 | EP0782070A1 Finite field inverter |
| 07/02/1997 | EP0782069A1 Pseudorandom number generator |
| 07/02/1997 | EP0781472A1 Multipurpose error correction calculation circuit |
| 07/02/1997 | EP0781470A1 Versatile error correction system |
| 07/01/1997 | US5644639 Device for carrying out a division |
| 07/01/1997 | US5644524 Iterative division apparatus, system and method employing left most one's detection and left most one's detection with exclusive or |
| 07/01/1997 | US5644522 Method, apparatus and system for multiply rounding using redundant coded multiply result |
| 07/01/1997 | US5644521 Comparator scheme |
| 07/01/1997 | US5644520 Accumulator circuit and method of use thereof |
| 07/01/1997 | US5644519 Method and apparatus for a multiply and accumulate circuit having a dynamic saturation range |
| 07/01/1997 | US5644517 Method for performing matrix transposition on a mesh multiprocessor architecture having multiple processor with concurrent execution of the multiple processors |
| 07/01/1997 | US5644253 Multiple-valued logic circuit |
| 06/26/1997 | WO1997022921A1 A method and apparatus for executing floating point and packed data instructions using a single register file |
| 06/26/1997 | CA2193196A1 Pseudorandom number generator |
| 06/25/1997 | EP0781012A2 Arithmetic unit |
| 06/25/1997 | EP0780846A2 Field programmable memory array |
| 06/25/1997 | EP0780759A1 Elimination of math overflow flag generation delay in an alu |
| 06/25/1997 | CN1152746A High speed modular multiplication method and device |
| 06/24/1997 | US5642306 Method and apparatus for a single instruction multiple data early-out zero-skip multiplier |
| 06/17/1997 | US5640578 Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section |
| 06/17/1997 | US5640554 Parallel merge and sort process method and system thereof |
| 06/17/1997 | US5640398 State machine architecture for concurrent processing of multiplexed data streams |
| 06/17/1997 | US5640336 Computational array and method for calculating multiple terms of a polynomial in a single computing element |
| 06/17/1997 | US5640105 Current mode null convention threshold gate |
| 06/12/1997 | WO1997021170A1 Method and system for performing a boolean operation on bit strings using a maximal bit slice |
| 06/11/1997 | EP0778518A1 Method of producing a parameter J0 associated with the implementation of modular operations according to the Montgomery method |
| 06/11/1997 | EP0777946A1 Method and apparatus for inserting source identification data into a video signal |
| 06/11/1997 | EP0777883A1 X.500 system and methods |
| 06/10/1997 | US5638503 Method and apparatus for generating bitmaps from outlines containing bezier curves |
| 06/10/1997 | US5638490 Fuzzy logic data processor |
| 06/10/1997 | US5638314 Dividing apparatus for use in a data processing apparatus |
| 06/10/1997 | US5638313 Booth multiplier with high speed output circuitry |
| 06/10/1997 | US5638309 Pseudo-random pattern generating circuit |
| 06/10/1997 | US5638272 Control unit for vehicle and total control system therefor |
| 06/05/1997 | WO1997020268A1 A parametrizable control module comprising first and second loadables counters, an electronic circuit comprising a plurality of such parametrized control modules, and a method for synthesizing such circuit |
| 06/05/1997 | WO1997020266A1 An improved pseudo-random generator |
| 06/05/1997 | DE19618098C1 Random bit sequence generation circuit |
| 06/05/1997 | DE19609078C1 Threshold logic circuit using neuron transistors |
| 06/04/1997 | EP0776501A1 Area and time efficient field extraction circuit |
| 06/03/1997 | US5636369 Fast pattern-detection machine and method |
| 06/03/1997 | US5636351 Performance of an operation on whole word operands and on operations in parallel on sub-word operands in a single processor |
| 06/03/1997 | US5636157 Modular 64-bit integer adder |
| 06/03/1997 | US5636156 Adder with improved carry lookahead structure |
| 06/03/1997 | US5636155 Arithmetic processor and arithmetic method |
| 06/03/1997 | US5636154 Digital operation unit |
| 06/03/1997 | US5635858 Zero-stopping incrementers |
| 05/28/1997 | EP0776046A1 SOI CMOS logic circuit with transfer gates |
| 05/28/1997 | EP0672273A4 Method and apparatus for encryption having a feedback register with selectable taps. |
| 05/27/1997 | US5634065 Data processing apparatus |
| 05/27/1997 | US5633979 Signal processing system involving a least squares method |
| 05/27/1997 | US5633829 Serial access memory device capable of controlling order of access to memory cell areas |
| 05/27/1997 | US5633820 Self-resetting CMOS parallel adder with a bubble pipelined architecture, tri-rail merging logic, and enhanced testability |
| 05/27/1997 | US5633819 Inexact leading-one/leading-zero prediction integrated with a floating-point adder |
| 05/27/1997 | US5633818 Method and apparatus for performing floating point arithmetic operation and rounding the result thereof |
| 05/27/1997 | US5633816 Random number generator with wait control circuitry to enhance randomness of numbers read therefrom |
| 05/27/1997 | US5633814 Non-modulo power of 2 frequency divider |
| 05/22/1997 | WO1997018652A1 Efficient cryptographic hash functions and methods for amplifying the security of hash functions and pseudo-random functions |
| 05/22/1997 | WO1997011423A3 A method of generating secret identification numbers |
| 05/21/1997 | EP0774711A2 A method and apparatus for sorting elements |
| 05/21/1997 | EP0359809B1 Apparatus and method for floating point normalization prediction |
| 05/20/1997 | US5632041 Computational apparatus |
| 05/20/1997 | US5631941 Register circuit |
| 05/20/1997 | US5631860 Carry Selecting system type adder |
| 05/20/1997 | US5631859 Floating point arithmetic unit having logic for quad precision arithmetic |
| 05/20/1997 | US5631858 System for obtaining strict solution in accordance with accuracy of approximate solutions |
| 05/20/1997 | US5631578 Programmable array interconnect network |
| 05/15/1997 | WO1997017652A1 Information processing apparatus and method |
| 05/15/1997 | DE19653565A1 Recursively divided adder with carry select |
| 05/14/1997 | EP0773499A1 Fastmultiplier for multiplying a digital signal to a periodic signal |
| 05/14/1997 | EP0772818A1 Apparatus and method for executing pop instructions |
| 05/14/1997 | EP0772817A1 EXECUTION UNIT ARCHITECTECTURE TO SUPPORT x86 INSTRUCTION SET AND x86 SEGMENTED ADDRESSING |
| 05/14/1997 | EP0772815A2 Method for performing signed division |
| 05/14/1997 | EP0772814A1 Incrementor/decrementor |
| 05/14/1997 | EP0772812A1 Bit searching through 8, 16, or 32 bit operands using a 32 bit data path |
| 05/14/1997 | EP0772810A1 Non-arithmetical circular buffer cell availability status indicator circuit |
| 05/14/1997 | EP0733233A4 Apparatus and method for signal processing |
| 05/14/1997 | CN1149734A Parallel treatment dividing circuit |
| 05/13/1997 | US5630162 Array processor dotted communication network based on H-DOTs |
| 05/13/1997 | US5630160 Floating point exponent compare using repeated two bit compare cell |
| 05/13/1997 | US5630123 Software system utilizing a filtered priority queue and method of operation |
| 05/13/1997 | US5630084 System for converting data in little endian to big endian and vice versa by reversing two bits of address referencing one word of four words |
| 05/13/1997 | US5630023 Signal processor |
| 05/13/1997 | US5629945 Electronic arithmetic unit with multiple error detection |
| 05/13/1997 | US5629886 Method and structure for providing fast propagation of a carry signal in a field programmable gate array |
| 05/13/1997 | US5629885 Squaring circuit for binary numbers |