| Patents for G06F 7 - Methods or arrangements for processing data by operating upon the order or content of the data handled (93,043) |
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| 07/27/1999 | US5928318 Clamping divider, processor having clamping divider, and method for clamping in division |
| 07/27/1999 | US5928317 Fast converter for left-to-right carry-free multiplier |
| 07/27/1999 | US5928316 Fused floating-point multiply-and-accumulate unit with carry correction |
| 07/27/1999 | US5928315 Apparatus and method for calculating Bc (mod n) |
| 07/27/1999 | US5928310 Digital device control method and system via linear function generator implementation using adder for intercept |
| 07/22/1999 | WO1999037029A1 High-speed evaluation of polynomials |
| 07/22/1999 | WO1997043709A9 Random number generator |
| 07/22/1999 | DE19847245A1 Combined arithmetic adder and logic unit |
| 07/21/1999 | EP0930564A1 Arithmetic unit and arithmetic method |
| 07/21/1999 | EP0929862A1 Logic elements for interlaced carry/borrow systems having a uniform layout |
| 07/21/1999 | CN1223401A 电子算盘 Electronic abacus |
| 07/20/1999 | US5926815 Binary sort access method and apparatus |
| 07/20/1999 | US5926642 RISC86 instruction set |
| 07/20/1999 | US5926407 Combined add/shift structure |
| 07/20/1999 | US5926406 System and method for calculating floating point exponential values in a geometry accelerator |
| 07/20/1999 | US5926396 Logic synthesis method, semiconductor integrated circuit and arithmetic circuit |
| 07/20/1999 | US5926057 Semiconductor device, circuit having the device, and correlation calculation apparatus, signal converter, and signal processing system utilizing the circuit |
| 07/15/1999 | WO1999035782A1 Leak-resistant cryptographic method and apparatus |
| 07/15/1999 | WO1999035564A1 An efficient way to produce a delayed version of a maximum length sequence |
| 07/14/1999 | EP0797806B1 Method for binary-oriented set sequencing |
| 07/13/1999 | US5924093 Virtual processor buffered merge sort for parallel applications |
| 07/13/1999 | US5924092 Computer system and method which sort array elements to optimize array modifications |
| 07/13/1999 | US5924091 Database system with improved methods for radix sorting |
| 07/13/1999 | US5923900 Circular buffer with n sequential real and virtual entry positions for selectively inhibiting n adjacent entry positions including the virtual entry positions |
| 07/13/1999 | US5923888 Multiplier for the multiplication of at least two figures in an original format |
| 07/13/1999 | US5923871 Multifunctional execution unit having independently operable adder and multiplier |
| 07/13/1999 | US5923579 Optimized binary adder and comparator having an implicit constant for an input |
| 07/13/1999 | US5923578 Data processing circuit |
| 07/13/1999 | US5923577 Method and apparatus for generating an initial estimate for a floating point reciprocal |
| 07/13/1999 | US5923575 Method for eletronically representing a number, adder circuit and computer system |
| 07/13/1999 | US5923574 Optimized, combined leading zeros counter and shifter |
| 07/08/1999 | WO1999034554A2 Administration and utilization of secret fresh random numbers in a networked environment |
| 07/08/1999 | WO1999034514A1 Logic circuit |
| 07/08/1999 | WO1999034281A1 System for computing the multiplicative inverse of an element of a galois field without using tables |
| 07/07/1999 | EP0928065A2 Multiported register file for coefficient use in filters |
| 07/07/1999 | EP0927928A1 Improved method of producing a parameter J0 associated with the implementation of modular operations according to the Montgomery method |
| 07/07/1999 | EP0927393A1 Digital signal processing integrated circuit architecture |
| 07/07/1999 | EP0927390A1 Data processing condition code flags |
| 07/07/1999 | EP0927388A1 Data processing apparatus registers |
| 07/07/1999 | EP0578821B1 Semiconductor device |
| 07/06/1999 | US5920498 Compression circuit of an adder circuit |
| 07/06/1999 | US5920497 Method and apparatus for performing a double precision operation using a single instruction type |
| 07/06/1999 | US5920493 Apparatus and method to determine a most significant bit |
| 07/01/1999 | WO1999033276A1 Device for multiplying with constant factors and use of said device for video compression (mpeg) |
| 07/01/1999 | WO1999033209A1 Method of providing and retrieving a data segment |
| 07/01/1999 | WO1999033184A2 Binary code converters and comparators |
| 07/01/1999 | WO1999033175A1 Digital signal filter using weightless neural techniques |
| 07/01/1999 | WO1999033019A1 Neural networks and neural memory |
| 07/01/1999 | WO1999032962A1 Weightless binary n-tuple thresholding hierarchies |
| 07/01/1999 | WO1999032961A1 Hamming value comparison for unweighted bit arrays |
| 07/01/1999 | WO1999022292A8 Fast regular multiplier architecture |
| 07/01/1999 | DE19826315A1 Comparators for two binary numbers |
| 06/30/1999 | CN1221186A Modulation device and method and distribution medium |
| 06/30/1999 | CN1221151A Electronic apparatus comprising memory protection device and method of protecting data in memory |
| 06/29/1999 | US5918252 Apparatus and method for generating a modulo address |
| 06/29/1999 | US5918062 Microprocessor including an efficient implemention of an accumulate instruction |
| 06/29/1999 | US5917742 Semiconductor arithmetic circuit |
| 06/29/1999 | US5917741 Method and apparatus for performing floating-point rounding operations for multiple precisions using incrementers |
| 06/29/1999 | US5917740 Apparatus for reducing a computational result to the range boundaries of a signed 16-bit integer in case of overflow |
| 06/29/1999 | US5917739 Calculating the average of four integer numbers rounded towards zero in a single instruction cycle |
| 06/29/1999 | US5917732 Arithmetic unit, correlation arithmetic unit and dynamic image compression apparatus |
| 06/29/1999 | US5917338 Area-efficient implication circuits for very dense Lukasiewicz logic arrays |
| 06/24/1999 | WO1999031601A1 Processor having multiple datapath instances |
| 06/24/1999 | WO1999031581A2 Method and apparatus for address analysis based on boolean logic |
| 06/24/1999 | WO1999031574A1 Implementation of multipliers in programmable arrays |
| 06/24/1999 | WO1999031573A1 Semiconductor circuit for arithmetic operation and method of arithmetic operation |
| 06/24/1999 | WO1999031562A2 Binary adder |
| 06/24/1999 | WO1999017220A3 Methods apparatus and computer program products for accumulating logarithmic values |
| 06/24/1999 | CA2312707A1 Processor having multiple datapath instances |
| 06/23/1999 | EP0924895A2 Encryption and decryption devices for public-key cryptosystems and recording medium with their processing programs recorded thereon |
| 06/23/1999 | EP0924601A2 Parallel data processing in a single processor |
| 06/23/1999 | EP0924600A1 Electronic apparatus comprising a memory protection device and a method for protecting data in a memory |
| 06/23/1999 | EP0924599A1 Method for generating random numbers |
| 06/23/1999 | EP0924598A2 Content addressable memory fifo with and without purging |
| 06/23/1999 | CA2254545A1 Multiported register file for coefficient use in filters |
| 06/23/1999 | CA2254543A1 Multiported register file for burst mode coefficient updating |
| 06/22/1999 | US5915247 Method for storing membership functions and related circuit for calculating a grade of membership of antecedents of fuzzy rules |
| 06/22/1999 | US5915079 Multi-path data processing pipeline |
| 06/22/1999 | US5914984 Method and device for pulse width modulation control |
| 06/22/1999 | US5914906 Field programmable memory array |
| 06/22/1999 | US5914892 Structure and method of array multiplication |
| 06/22/1999 | US5914868 Multiplier and neural network synapse using current mirror having low-power mosfets |
| 06/17/1999 | WO1999030458A1 Transformation methods for optimizing elliptic curve cryptographic computations |
| 06/17/1999 | WO1999030250A1 Information processing system, enciphering/deciphering system, system lsi, and electronic apparatus |
| 06/17/1999 | CA2310588A1 Transformation methods for optimizing elliptic curve cryptographic computations |
| 06/16/1999 | EP0923077A1 Method and device for VLC (d,k;m,n;r) coding |
| 06/16/1999 | EP0922332A1 Frequency dividing circuit |
| 06/16/1999 | CN1219477A Bar-coded money and corresponding automatic redeeming device and system |
| 06/15/1999 | US5912909 Method and apparatus for efficient implementation of checksum calculations |
| 06/15/1999 | US5912904 In a coprocessor apparatus |
| 06/15/1999 | US5912833 Carry increment adder using clock phase |
| 06/15/1999 | US5912832 Fast n-bit by n-bit multipliers using 4-bit by 4-bit multipliers and cascaded adders |
| 06/15/1999 | US5912831 Process and system for adding or substracting symbols in any base without converting to a common base |
| 06/15/1999 | US5912830 System and method for conditionally calculating exponential values in a geometry accelerator |
| 06/15/1999 | CA2055882C Binary carry circuitry |
| 06/10/1999 | WO1999014880A3 A method and device for executing a decrypting mechanism through calculating a standardized modular exponentiation for thwarting timing attacks |
| 06/09/1999 | EP0921462A2 Arithmetic unit and data processing unit |
| 06/09/1999 | EP0921461A2 Bit-Depth Increase by bit replication |
| 06/09/1999 | EP0871932A4 Two-digit hybrid radix year numbers for year 2000 and beyond |
| 06/09/1999 | EP0789870A4 Method and apparatus for custom operations of a processor |