| Patents for G06F 7 - Methods or arrangements for processing data by operating upon the order or content of the data handled (93,043) |
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| 04/15/1999 | WO1999018573A1 Recording/reproducing device and recording/reproducing method |
| 04/15/1999 | WO1999018423A1 Object identification system applications |
| 04/14/1999 | EP0909055A2 Pseudo-random number generating method and apparatus therefor |
| 04/14/1999 | EP0909038A2 Decoding of convolutional code with floating point ACS processing |
| 04/14/1999 | EP0909033A2 Rectifying transfer gate circuit |
| 04/14/1999 | EP0908834A1 Method and apparatus for proving system properties |
| 04/13/1999 | US5894568 Apparatus and method for computing a difference in a digital processing system |
| 04/13/1999 | US5894427 Technique for concurrent detection of bit patterns |
| 04/08/1999 | WO1999017220A2 Methods apparatus and computer program products for accumulating logarithmic values |
| 04/08/1999 | WO1999016634A1 Method and device for producing an error signal in a motor vehicle |
| 04/08/1999 | DE19743856A1 Radioactive random number generator |
| 04/07/1999 | EP0906678A1 Improved cryptographically secure pseudo-random bit generator for fast and secure encryption |
| 04/06/1999 | USRE36183 System for rearranging sequential data words from an initial order to an arrival order in a predetermined order |
| 04/06/1999 | USRE36181 Pseudorandom number generation and crytographic authentication |
| 04/06/1999 | US5893145 System and method for routing operands within partitions of a source register to partitions within a destination register |
| 04/06/1999 | US5892960 Method and computer system for processing a set of data elements on a sequential processor |
| 04/06/1999 | US5892699 Method and apparatus for optimizing dependent operand flow within a multiplier using recoding logic |
| 04/06/1999 | US5892698 2's complement floating-point multiply accumulate unit |
| 04/06/1999 | US5892697 Method and apparatus for handling overflow and underflow in processing floating-point numbers |
| 04/06/1999 | US5890800 Method and device for the division of elements of a Galois field |
| 04/06/1999 | CA2113140C Rank order filter |
| 04/01/1999 | WO1999016175A1 Semiconductor integrated circuit and data processing system |
| 04/01/1999 | DE19840985A1 Drive force regulator for motor vehicle with continuously variable transmission |
| 03/31/1999 | EP0905636A2 Local sorting of downloaded tables |
| 03/31/1999 | EP0905611A2 Pseudorandom number generating method and pseudorandom number generator |
| 03/31/1999 | CN1212777A Method for processing leaf items, especially bank notes |
| 03/31/1999 | CN1212592A PN code generating device and mobile radio communication system |
| 03/30/1999 | US5889979 Transparent data-triggered pipeline latch |
| 03/30/1999 | US5889822 Signal processor with reduced complexity, and receiver comprising such a signal processor |
| 03/30/1999 | US5889746 Information recording medium, apparatus for recording the same and apparatus for reproducing the same |
| 03/30/1999 | US5889693 CMOS sum select incrementor |
| 03/30/1999 | US5889692 Fast determination of carry inputs from lower order product for radix-8 odd/even multiplier array |
| 03/30/1999 | US5889691 Apparatus and method for a multiplier unit with high component utilization |
| 03/30/1999 | US5889690 Multiply-add unit and data processing apparatus using it |
| 03/30/1999 | US5889689 Hierarchical carry-select, three-input saturation |
| 03/30/1999 | US5889665 Analogue multiplier using MOSFETs in nonsaturation region and current mirror |
| 03/30/1999 | CA2249067A1 Local sorting of downloaded tables |
| 03/25/1999 | WO1999014880A2 A method and device for executing a decrypting mechanism through calculating a standardized modular exponentiation for thwarting timing attacks |
| 03/25/1999 | WO1999014858A1 Quantum computer |
| 03/25/1999 | WO1999014661A1 Parallel prefix operations in asynchronous processors |
| 03/25/1999 | WO1999014614A1 Electron devices for single electron and nuclear spin measurement |
| 03/25/1999 | WO1999005685A8 Self-tuning system for industrial surveillance |
| 03/25/1999 | DE19820050C1 Circuit arrangement with single electron components in CMOS logic circuit application |
| 03/25/1999 | CA2304185A1 Quantum computer |
| 03/25/1999 | CA2304045A1 Electron devices for single electron and nuclear spin measurement |
| 03/24/1999 | EP0903672A2 Cellular automaton and its use |
| 03/24/1999 | EP0903665A2 Physical random number generator, method of generating physical random numbers and physical random number storing medium |
| 03/24/1999 | EP0903664A2 Floating-point processor with operand-format precision greater than execution precision |
| 03/24/1999 | EP0704124A4 A cryptographic method |
| 03/24/1999 | EP0606368B1 Packet processing method and apparatus |
| 03/24/1999 | CA2247910A1 Pseudorandom number generating method and pseudorandom number generator |
| 03/23/1999 | US5887274 Restartable fast DB2 tablespace reorganization method |
| 03/23/1999 | US5887160 Method and apparatus for communicating integer and floating point data over a shared data path in a single instruction pipeline processor |
| 03/23/1999 | US5887137 Data processing apparatus having a sorting unit to provide sorted data to a processor |
| 03/23/1999 | US5886915 Method and apparatus for trading performance for precision when processing denormal numbers in a computer system |
| 03/23/1999 | US5886911 Fast calculation method and its hardware apparatus using a linear interpolation operation |
| 03/23/1999 | CA2144240C Analog multiplier using multitail cell |
| 03/18/1999 | WO1999013578A1 Non-linear counting device |
| 03/18/1999 | WO1999013572A1 Random signal generator |
| 03/18/1999 | DE19738115C1 Schaltungsanordnung mit Einzelelektron-Bauelementen, Verfahren zu deren Betrieb und Anwendung des Verfahrens zur Addition von Binärzahlen Circuit arrangement having single-electron components, process for their operation and use of the method for addition of binary numbers |
| 03/17/1999 | EP0902361A2 Single-chip CPU and microcomputer |
| 03/17/1999 | EP0902360A2 Apparatus for read/write-access to registers in a central processing unit |
| 03/17/1999 | EP0902359A1 Method for performing integer division on a modulo arithmetic coprocessor |
| 03/17/1999 | EP0902358A2 Division circuit and method |
| 03/17/1999 | CN1211329A Method of modifying the instruction set of a smart card |
| 03/17/1999 | CN1211328A Method of generating signal amplitude responsive to desired function, and converter |
| 03/16/1999 | US5884092 System for maintaining fixed-point data alignment within a combination CPU and DSP system |
| 03/16/1999 | US5884069 Computer and a method of operating a computer to combine data values within a singularly addressable data string |
| 03/16/1999 | US5883825 Reduction of partial product arrays using pre-propagate set-up |
| 03/16/1999 | US5883824 Parallel adding and averaging circuit and method |
| 03/16/1999 | US5883677 Method and apparatus for managing multiple outside video service providers |
| 03/16/1999 | CA2107771C Multiple accumulator fractional n synthesis with series recombination |
| 03/11/1999 | WO1999012212A2 Lone-electron circuit arrangement, operating mode, and application for adding binary numbers |
| 03/11/1999 | WO1999012093A1 Multiplier sign extension |
| 03/11/1999 | WO1998056005A3 Method and device for data sequence manipulation |
| 03/11/1999 | DE19739768A1 Verfahren und Einrichtung zum Erzeugen einer Folge von mehrstelligen Binärcodes Method and apparatus for generating a sequence of multi-digit binary code |
| 03/10/1999 | EP0901291A1 Yuv-rgb digital conversion circuit and picture display device and electronic equipment using the same |
| 03/10/1999 | EP0901236A2 PN code generator |
| 03/10/1999 | EP0901230A1 Adiabatic charging logic circuit |
| 03/10/1999 | EP0901106A2 System and method using mode bits to support multiple coding standards |
| 03/10/1999 | EP0901069A2 A method of and an apparatus for generating pseudo-random numbers |
| 03/10/1999 | EP0901068A2 Near-orthogonal dual-mac instruction set architecture with minimal encoding bits |
| 03/10/1999 | EP0795154A4 Microprocessor with compare operation of composite operands |
| 03/09/1999 | US5881301 Inverse modeller |
| 03/09/1999 | US5881261 Processing system that rapidly indentifies first or second operations of selected types for execution |
| 03/09/1999 | US5881259 Input operand size and hi/low word selection control in data processing systems |
| 03/09/1999 | US5881217 Input comparison circuitry and method for a programmable state machine |
| 03/09/1999 | US5881076 Comparator utilizing redundancy |
| 03/09/1999 | US5880986 Method and apparatus for reducing power usage within a domino logic unit |
| 03/09/1999 | US5880985 Efficient combined array for 2n bit n bit multiplications |
| 03/09/1999 | US5880984 Method and apparatus for performing high-precision multiply-add calculations using independent multiply and add instruments |
| 03/09/1999 | US5880983 Floating point split multiply/add system which has infinite precision |
| 03/09/1999 | US5880982 Error detecting digital arithmetic circuit |
| 03/09/1999 | US5880981 Method and apparatus for reducing the power consumption in a programmable digital signal processor |
| 03/09/1999 | US5880979 System for providing the absolute difference of unsigned values |
| 03/09/1999 | US5880978 Method and apparatus for creating an output vector from an input vector |
| 03/09/1999 | US5880968 Method and apparatus for reducing power usage within a domino logic unit |
| 03/09/1999 | US5880671 Flexible circuitry and method for detecting signal patterns on a bus |
| 03/09/1999 | US5880618 CMOS differential voltage controlled logarithmic attenuator and method |
| 03/04/1999 | WO1999010802A1 A reconfigurable arithmetic datapath |