| Patents for H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass (25,714) |
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| 02/28/2002 | US20020025015 Recovery circuit generating low jitter reproduction clock |
| 02/28/2002 | US20020024367 Method and apparatus for digital delay locked loop circuits |
| 02/28/2002 | US20020024366 Semiconductor device incorporating clock generating circuit |
| 02/28/2002 | US20020024363 Sample-and-hold amplifier circuit and pipelined A/D and D/A converters using sample hold amplification circuit |
| 02/28/2002 | US20020024360 Method for buffering an input signal |
| 02/28/2002 | DE10036722C1 Frequency doubling circuit for data transmission bus has input signal and processed input signal combined via Exclusive-OR gate |
| 02/26/2002 | US6351756 Clock signal multiplier circuit for a clock signal generator circuit |
| 02/26/2002 | US6351283 Charge amplifier for MOS imaging array |
| 02/26/2002 | US6351191 Differential delay cell with common delay control and power supply |
| 02/26/2002 | US6351171 Accelerated interconnect transmission via voltage clamping towards toggle point |
| 02/26/2002 | US6351169 Internal clock signal generating circuit permitting rapid phase lock |
| 02/26/2002 | US6351167 Integrated circuit with a phase locked loop |
| 02/26/2002 | US6351154 Phase detector |
| 02/26/2002 | US6351153 Phase detector with high precision |
| 02/26/2002 | US6351136 Passive voltage limiter |
| 02/21/2002 | WO2002015403A1 Synchronizer with zero metastability |
| 02/21/2002 | WO2002015401A2 Voltage stabilized low level driver |
| 02/21/2002 | WO2002015396A1 Digital pulse shaper with variable weighting function |
| 02/21/2002 | US20020023253 Zero hold time circuit for high speed bus applications |
| 02/21/2002 | US20020021775 Circuit for generating an output phase signal with a variable phase shift relative to a reference phase |
| 02/21/2002 | US20020021161 Electrical circuit having inverters being serially connected together in a cascade |
| 02/21/2002 | US20020021160 Pulse generator |
| 02/21/2002 | US20020021159 Delay circuit and method |
| 02/21/2002 | US20020021158 Comparator for determining process variations |
| 02/21/2002 | US20020021157 Variable delay circuit and semiconductor integrated circuit device |
| 02/21/2002 | US20020021155 Circuit configuration for compensating runtime and pulse-duty-factor differences between two input signals |
| 02/21/2002 | US20020021154 Circuit and method for multi-phase alignment |
| 02/21/2002 | US20020021153 Clock controlling method and circuit |
| 02/21/2002 | US20020021152 DLL circuit and method of generating timing signals |
| 02/21/2002 | US20020021149 Input buffer circuit for transforming pseudo differential signals into full differential signals |
| 02/21/2002 | US20020021147 Sense amplifiers having gain control circuits therein that inhibit signal oscillations |
| 02/21/2002 | DE10039421A1 Phase detector providing phase difference between binary input signals uses 2 Exclusive-OR elements receiving both input signals with their output signals subtracted to provide regulating voltage |
| 02/20/2002 | EP1180689A2 Frequency determination circuit for a data processing unit |
| 02/20/2002 | CN1336561A Multiple optical fiber and digital delay wire |
| 02/19/2002 | US6349121 Baseband data slicing method and apparatus |
| 02/19/2002 | US6348882 5-ary receiver utilizing common mode insensitive differential offset comparator |
| 02/19/2002 | US6348839 Delay circuit for ring oscillator |
| 02/19/2002 | US6348828 Clock enable circuit for use in a high speed reprogrammable delay line incorporating glitchless enable/disable functionality |
| 02/19/2002 | US6348827 Programmable delay element and synchronous DRAM using the same |
| 02/19/2002 | US6348826 Digital variable-delay circuit having voltage-mixing interpolator and methods of testing input/output buffers using same |
| 02/19/2002 | US6348821 Frequency doubler with 50% duty cycle output |
| 02/19/2002 | US6348816 Tracking percent overload signal as indicator of output signal magnitude |
| 02/14/2002 | WO2002013385A1 Method and apparatus for a digital clock multiplication circuit |
| 02/14/2002 | WO2002013201A2 Circuit and method for multi-phase alignment |
| 02/14/2002 | WO2001047111A3 Capacitively coupled re-referencing circuit with positive feedback |
| 02/14/2002 | WO2001033828A3 Slip-detecting phase detector and method for improving phase-lock loop lock time |
| 02/14/2002 | US20020017951 Preamplification circuit |
| 02/14/2002 | US20020017944 Method and apparatus for glitch protection for input buffers in a source-synchronous environment |
| 02/14/2002 | US20020017939 Clock generation circuit, control method of clock generation circuit, clock reproducing circuit, semiconductor memory device, and dynamic random access memory |
| 02/14/2002 | US20020017938 Clock generator with programmable non-overlapping-clock-edge capability |
| 02/14/2002 | US20020017936 Apparatus and method for edge based duty cycle conversion |
| 02/14/2002 | US20020017928 Comparator circuit |
| 02/14/2002 | US20020017926 Frequency determination circuit for a data processing unit |
| 02/14/2002 | US20020017925 Oscillation stop detection circuit |
| 02/14/2002 | US20020017918 Pulse generation circuit and a drive circuit |
| 02/14/2002 | DE10131651A1 Verzögerungsregelschleife zur Verwendung in einem Halbleiterspeicherbauteil Delay-locked loop for use in a semiconductor memory device |
| 02/14/2002 | CA2417021A1 Method and apparatus for a digital clock multiplication circuit |
| 02/13/2002 | CN1335678A Phase-shift circuit and FM detecting circuit |
| 02/13/2002 | CN1335677A Clock control method and electric circuit |
| 02/12/2002 | US6347046 Current driver circuit with a damping circuit |
| 02/12/2002 | US6346841 Pulse generator |
| 02/12/2002 | US6346836 Synchronizing stage |
| 02/12/2002 | US6346835 Power-on reset signal preparing circuit |
| 02/12/2002 | US6346833 Frequency multiplier circuit |
| 02/12/2002 | US6346823 Pulse generator for providing pulse signal with constant pulse width |
| 02/07/2002 | WO2002011284A1 Semiconductor integrated circuit |
| 02/07/2002 | US20020016936 Buffer device |
| 02/07/2002 | US20020016932 Semiconductor integrated circuit and semiconductor apparatus system |
| 02/07/2002 | US20020015461 Wideband communication using delay line clock multiplier |
| 02/07/2002 | US20020015338 Delay locked loop for use in semiconductor memory device |
| 02/07/2002 | US20020014909 Pump circuit boosting a supply voltage |
| 02/07/2002 | US20020014903 Semiconductor device using complementary clock and signal input state detection circuit used for the same |
| 02/07/2002 | US20020014902 Low jitter high speed CMOS to CML clock converter |
| 02/07/2002 | US20020014901 DLL circuit and DLL control method |
| 02/06/2002 | EP1178626A2 Digital phase control using first and second delay lines |
| 02/06/2002 | EP1178610A2 Delay circuit for ring oscillator with power supply noise compensation |
| 02/06/2002 | EP1178609A2 Phase detector |
| 02/06/2002 | EP1177628A1 Circuit arrangement for generating current impulses in the supply current of integrated circuits |
| 02/06/2002 | CN1334987A Level shift circuit |
| 02/05/2002 | US6344957 Overshoot/undershoot prevention device and overshoot/undershoot prevention method |
| 02/05/2002 | US6344762 Bias circuit for a low voltage differential circuit |
| 02/05/2002 | US6344761 Current comparison type latch |
| 02/04/2002 | CA2354780A1 Digital display jitter correction apparatus and method |
| 01/31/2002 | WO2002009374A2 Decoding of asynchronous data signals, using calculation of derivates |
| 01/31/2002 | WO2002009282A1 Three-terminal inverting hysteretic transistor switch |
| 01/31/2002 | WO2002009281A2 5-ary receiver utilizing common mode insensitive differential offset comparator |
| 01/31/2002 | US20020012413 Circuit for generating an inverse signal of a digital signal with a minimal delay difference between the inverse signal and the digital signal |
| 01/31/2002 | US20020012040 Scanning-sync signal detecting circuit for laser scanner |
| 01/31/2002 | US20020011891 Switching control circuit |
| 01/31/2002 | US20020011889 Semiconductor integral circuit |
| 01/31/2002 | US20020011887 Semiconductor buffer circuit with a transition delay circuit |
| 01/31/2002 | US20020011882 Power-on reset signal preparing circuit |
| 01/31/2002 | US20020011875 Cmos buffer for driving a large capacitive load |
| 01/31/2002 | US20020011872 Voltage level shifter circuit |
| 01/31/2002 | DE10035636A1 Circuit, especially semiconducting circuit, memory device, DRAM element or similar has protection device that analyzes input signal for noise, suppresses signal transfer if noise is present. |
| 01/31/2002 | DE10035424A1 Buffer memory has multiplexing to latches improves stability without extra latches |
| 01/30/2002 | CN1333598A Fixed time equation divided circuit and signal control method and device |
| 01/29/2002 | US6343096 Clock pulse degradation detector |
| 01/29/2002 | US6342801 Duty cycle correction circuit of delay locked loop |
| 01/29/2002 | US6342799 Error correcting programmable pulse generator |