Patents
Patents for H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass (25,714)
09/2001
09/11/2001US6288577 Active fail-safe detect circuit for differential receiver
09/11/2001US6288576 Fast pre-amplifier for an interface arrangement
09/11/2001US6288575 Pseudo-differential current sense amplifier with hysteresis
09/07/2001WO2001065681A2 Fractional-phase locked loop
09/06/2001US20010019283 High-speed dynamic latch
09/06/2001US20010019282 Pulse generator
09/06/2001DE10006236A1 Anordnung zum Generieren von Signalimpulsen mit definierten Pulslängen in einem Baustein mit BIST-Funktion Arrangement for generating signal pulses with pulse lengths defined in a block with BIST function
09/05/2001EP1130776A2 Load equalization in digital delay interpolators
09/05/2001CN1311443A Band-gas voltage comparator used for low voltage testing circuit
09/04/2001US6285723 Timing signal generation circuit
09/04/2001US6285262 Frequency divider, a phase lock oscillator and a flip-flop circuit using the frequency divider
09/04/2001US6285230 Input buffer circuit with adjustable delay via an external power voltage
09/04/2001US6285229 Digital delay line with low insertion delay
09/04/2001US6285228 Integrated circuit for generating a phase-shifted output clock signal from a clock signal
09/04/2001US6285226 Duty cycle correction circuit and method
09/04/2001US6285225 Delay locked loop circuits and methods of operation thereof
09/04/2001US6285206 Comparator circuit
09/04/2001US6285184 Speed and position signal generator
08/2001
08/30/2001US20010018754 Configuration for generating signal impulses of defined lengths in a module with a bist-function
08/30/2001US20010017563 Pulse generator
08/30/2001US20010017558 Semiconductor integrated circuit having a clock recovery circuit
08/28/2001US6282253 Post-filtered recirculating delay-locked loop and method for producing a clock signal
08/28/2001US6282133 Semiconductor memory device having a delay circuit for generating a read timing
08/28/2001US6282129 Memory devices and memory reading methods
08/28/2001US6281759 Digital frequency generation method and apparatus
08/28/2001US6281741 Integrated circuit including current mirror and dual-function transistor
08/28/2001US6281735 Voltage clamping circuits for limiting the voltage range of an input signal
08/28/2001US6281728 Delay locked loop circuit
08/28/2001US6281726 Device and method in a delay locked loop for generating quadrature and other off-phase clocks with improved resolution
08/28/2001US6281725 Semiconductor integrated circuit having a clock recovery circuit
08/28/2001US6281716 Potential detect circuit for detecting whether output potential of potential generation circuit has arrived at target potential or not
08/23/2001WO2001061853A1 High noise rejection voltage-controlled ring oscillator architecture
08/23/2001US20010016022 Delay time adjusting circuit comprising frequency dividers having different frequency division rates
08/23/2001US20010015666 Semiconductor integrated circuit device, semiconductor memory system and clock synchronous circuit
08/23/2001US20010015664 Delay time adjusting method of delaying a phase of an output signal until a phase difference between an input signal and the output signal becomes an integral number of periods other than zero
08/22/2001EP1126618A2 Clock signal generator and communication device using the same
08/22/2001EP1126609A1 Circuit for generating signal pulses with defined pulse length in a device with BIST-function
08/22/2001EP1126352A1 Bandgap voltage comparator used as a low voltage detection circuit
08/22/2001EP1125297A1 Comparators, memory devices, comparison methods and memory reading methods
08/22/2001CN1309834A Timing device and method
08/22/2001CN1309468A Delay device calibrated by phase-locked loop and its calibration method
08/21/2001US6278638 Pulse generator circuit and semiconductor memory provided with the same
08/21/2001US6278331 System and method for compensating wafer parameters
08/21/2001US6278310 Semiconductor buffer circuit with a transition delay circuit
08/21/2001US6278309 Method of controlling a clock signal and circuit for controlling a clock signal
08/21/2001US6278307 Method and apparatus for 50% duty-cycle programmable divided-down clock with even and odd divisor rates
08/21/2001CA2196953C Method and apparatus for detection of missing pulses from a repetitive pulse train
08/16/2001WO2001059928A1 Balanced circuit arrangement
08/16/2001US20010014048 Delay locked loop with delay control unit for noise elimination
08/16/2001DE10004079A1 Komparatorschaltungsanordnung und Verfahren zum Kompensieren der Offsetspannung eines Komparators Comparator circuit and method for compensating the offset voltage of a comparator
08/16/2001DE10003532C1 Taktgenerator Clock generator
08/15/2001CN1308312A Buzzer driving circuit
08/14/2001US6275555 Digital delay locked loop for adaptive de-skew clock generation
08/14/2001US6275546 Glitchless clock switch circuit
08/14/2001US6275394 Input circuit
08/14/2001US6275107 Differential amplifier circuit and pull up-type differential driver
08/14/2001US6275101 Phase noise reduction circuits
08/14/2001US6275091 Clock signal control circuit and method and synchronous delay circuit
08/14/2001US6275086 Clock signal generator for an integrated circuit
08/14/2001US6275085 Comparator for determining process variations
08/14/2001US6275084 Phase modulated input/output circuit
08/14/2001US6275074 System for propagating a digital signal through a slew-rate limited node and method of operation
08/14/2001US6275073 Differential input circuit
08/14/2001US6275068 Programmable clock delay
08/14/2001US6275015 Circuit for reducing input voltage
08/09/2001WO2001001266A8 Digital delay locked loop with output duty cycle matching input duty cycle
08/09/2001US20010013101 Delay adjustment circuit and a clock generating circuit using the same
08/09/2001US20010011930 Nonlinear transmission line waveform generator
08/09/2001US20010011916 Clock signal generator for an integrated circuit
08/09/2001DE10100497A1 Ein einen niedrigen Verdrahtungszeitversatz aufweisendes Taktnetzwerk mit Strommoduspuffer A low wiring skew clock network exhibiting current mode buffer
08/08/2001EP0824789B1 Clock generator for cmos circuits with dynamic registers
08/07/2001US6272439 Programmable delay path circuit and operating point frequency detection apparatus
08/07/2001US6272185 Method and apparatus for performing data pulse detection
08/07/2001US6272181 Method and device for the aggregation of signals from sampling values
08/07/2001US6271711 Supply independent biasing scheme
08/07/2001US6271702 Clock circuit for generating a delay
08/07/2001US6271698 Method and apparatus for correcting imperfectly equalized bipolar signals
08/07/2001US6271697 Semiconductor integrated circuit device
08/07/2001US6271696 Phase adjustment circuit
08/07/2001US6271691 Chopper type voltage comparison circuit
08/07/2001US6271690 Discriminator
08/07/2001US6271682 Method and apparatus for high-speed edge-programmable timing signal generator
08/02/2001US20010010479 Integrated circuit having a comparator circuit including at least one differential amplifier
08/02/2001US20010010478 Level detection by voltage addition/subtraction
08/02/2001US20010010475 Clock generation circuit
08/02/2001DE10000758A1 Impulserzeuger Pulse generator
08/02/2001CA2297713A1 Method and apparatus for distributed synchronous clocking
08/01/2001EP1120914A1 Pulse generator
08/01/2001EP1120913A1 Method and apparatus for timing control
08/01/2001EP1120912A1 Method and apparatus for timing control
08/01/2001EP1119901A1 Frequency to frequency de-randomiser circuit
07/2001
07/31/2001US6269051 Semiconductor device and timing control circuit
07/31/2001US6268764 Bandgap voltage comparator used as a low voltage detection circuit
07/31/2001US6268757 Semiconductor device having capacitor that reduce fluctuation of power supply
07/31/2001US6268753 Delay element that has a variable wide-range delay capability
07/26/2001US20010009384 Clock period sensing circuit
07/26/2001DE10064206A1 Delay lock loop for use in semiconductor memory device has OR gate which performs OR operation of output signals of bidirectional delay blocks, and outputs signal as final internal clock signal
07/25/2001EP1119103A1 Clock signal supply
07/25/2001CN1305265A Input filtering stage of filter data stream and method of filter data stream
07/24/2001US6265924 Non-uniform delay stages to increase the operating frequency range of delay lines