| Patents for H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass (25,714) |
|---|
| 06/12/2001 | US6246704 Automatic on-chip clock tuning methodology and circuitry |
| 06/12/2001 | US6246278 High speed single phase to dual phase clock divider |
| 06/12/2001 | US6246276 Clock signal cleaning circuit |
| 06/12/2001 | US6246275 Multi-phase programmable clock generator |
| 06/12/2001 | US6246274 Semiconductor device capable of trimming minimum delay time and maximum delay time of an output signal |
| 06/12/2001 | US6246272 Power supply voltage detecting apparatus |
| 06/12/2001 | US6246271 Frequency multiplier capable of generating a multiple output without feedback control |
| 06/12/2001 | US6246268 CMOS integrated signal detection circuit with high efficiency and performance |
| 06/07/2001 | US20010002881 Oscillator circuit |
| 06/07/2001 | US20010002799 Method of controlling a clock signal and circuit for controlling a clock signal |
| 06/07/2001 | DE10034906A1 Dynamic logic entry latch for microprocessor, evaluates clock signal type and generates pulse for driving logic circuit to produce dynamic output signal |
| 06/06/2001 | CN1066825C Decision circuit operable at a wide range of voltage |
| 06/05/2001 | US6243784 Method and apparatus for providing precise circuit delays |
| 06/05/2001 | US6243031 Selectable delay circuit having immunity to variations in fabrication and operating condition for write precompensation in a read/write channel |
| 06/05/2001 | US6242961 Methods and circuits for restoration of a drooped DC signal |
| 06/05/2001 | US6242960 Internal clock signal generating circuit employing pulse generator |
| 06/05/2001 | US6242959 Programmable delay circuit and method with dummy circuit compensation |
| 06/05/2001 | US6242954 Timing clock generation circuit using hierarchical DLL circuit |
| 06/05/2001 | US6242953 Multiplexed synchronization circuits for switching frequency synthesized signals |
| 06/05/2001 | US6242908 Detection of passing magnetic articles while adapting the detection threshold |
| 05/31/2001 | WO2001039189A1 Device for writing information onto an information carrier |
| 05/31/2001 | WO2000043849A3 Electronic phase-locking loop (pll) |
| 05/31/2001 | US20010002207 Signal canceling method and device |
| 05/31/2001 | DE10054141A1 Delay control circuit for synchronous dynamic direct access memory has delay model for delaying external clock signal according to asymmetry, control signal generator, two delay devices |
| 05/31/2001 | DE10052988A1 Clock distribution module of digital system, has couplers in HF clock provision unit which transfer HF signals to each H tree configured nodes |
| 05/30/2001 | EP1104110A2 Phase-combining circuit and timing signal generator circuit for carrying out a high-speed signal transmission |
| 05/30/2001 | EP1104105A2 Electronic circuit with clock generating circuit |
| 05/29/2001 | US6239642 Integrated circuits with variable signal line loading circuits and methods of operation thereof |
| 05/29/2001 | US6239641 Delay locked loop using bidirectional delay |
| 05/29/2001 | US6239637 Method and apparatus for transmitting an electrical signal featuring pulse edge compression |
| 05/29/2001 | US6239635 Self-timing control circuit |
| 05/29/2001 | US6239627 Clock multiplier using nonoverlapping clock pulses for waveform generation |
| 05/29/2001 | US6239620 Method and apparatus for generating true/complement signals |
| 05/29/2001 | US6239618 Buffer with fast edge propagation |
| 05/29/2001 | US6239616 Programmable delay element |
| 05/25/2001 | WO2001037427A1 Digital frequency monitoring |
| 05/25/2001 | CA2388662A1 Digital frequency monitoring |
| 05/24/2001 | US20010001601 Delayed locked loop implementation in a synchronous dynamic random access memory |
| 05/24/2001 | US20010001544 Voltage divider circuit |
| 05/23/2001 | EP1102402A1 Level adjustment circuit and data output circuit thereof |
| 05/23/2001 | DE19953351C1 Bidirectional pulse source has 2 current sources connected in series via 2 switches controlled respectively by leading and trailing pulse flanks and 2 intermediate diodes |
| 05/22/2001 | US6236695 Output buffer with timing feedback |
| 05/22/2001 | US6236393 Interface circuit and liquid crystal driving circuit |
| 05/22/2001 | US6236248 Output buffer circuit |
| 05/22/2001 | US6236243 Negative voltage level detection circuit |
| 05/17/2001 | US20010001231 Comparator circuit |
| 05/17/2001 | DE19948892A1 Impulsdetektor und Verfahren zur Detektion von sinusförmigen Impulsen Pulse detector and method for detecting of sinusoidal pulses |
| 05/17/2001 | DE10056396A1 Waveform shaping circuit has simultaneous line stages between input, output nodes, current mirror circuits, capacitance device coupled to mirror circuit(s) and output node |
| 05/16/2001 | EP0818079B1 Timing generator for automatic test equipment operating at high data rates |
| 05/15/2001 | US6232842 Amplifying circuit and optical receiver comprising the same |
| 05/15/2001 | US6232813 Phase locked loop integrated circuits having fuse-enabled and fuse-disabled delay devices therein |
| 05/15/2001 | US6232812 Integrated circuit delay lines having programmable and phase matching delay characteristics |
| 05/15/2001 | US6232809 Differential input comparator with double sided hysteresis |
| 05/15/2001 | US6232807 Pulse generating circuit |
| 05/15/2001 | US6232806 Multiple-mode clock distribution apparatus and method with adaptive skew compensation |
| 05/15/2001 | US6232805 Buffer circuit with voltage clamping and method |
| 05/15/2001 | US6232804 Sample hold circuit having a switch |
| 05/15/2001 | US6232801 Comparators and comparison methods |
| 05/15/2001 | US6232800 Differential sense amplifier circuit and dynamic logic circuit using the same |
| 05/15/2001 | US6232797 Integrated circuit devices having data buffer control circuitry therein that accounts for clock irregularities |
| 05/15/2001 | US6232796 Apparatus and method for detecting two data bits per clock edge |
| 05/15/2001 | CA2253583C Phase locked loop |
| 05/10/2001 | WO2001033828A2 Slip-detecting phase detector and method for improving phase-lock loop lock time |
| 05/10/2001 | US20010000952 Clock control method and circuit |
| 05/10/2001 | DE10048538A1 Schnellschaltender Komparator mit Hysterese Quick switching-type comparator with hysteresis |
| 05/09/2001 | EP1097513A1 Clock pulse degradation detector |
| 05/08/2001 | US6229372 Active clamp network for multiple voltages |
| 05/08/2001 | US6229367 Method and apparatus for generating a time delayed signal with a minimum data dependency error using an oscillator |
| 05/08/2001 | US6229364 Frequency range trimming for a delay line |
| 05/08/2001 | US6229363 Semiconductor device |
| 05/08/2001 | US6229360 High speed synchronization circuit in semiconductor integrated circuit |
| 05/08/2001 | US6229359 Low phase noise clock multiplication |
| 05/08/2001 | US6229358 Delayed matching signal generator and frequency multiplier using scaled delay networks |
| 05/08/2001 | US6229350 Accurate, fast, and user programmable hysteretic comparator |
| 05/08/2001 | US6229347 Circuit for evaluating an asysmetric antenna effect |
| 05/08/2001 | US6229346 High frequency supply compatible hysteresis comparator with low dynamics differential input |
| 05/08/2001 | US6229345 High speed charge-pump |
| 05/08/2001 | US6229344 Phase selection circuit |
| 05/03/2001 | WO2001031798A1 Communications terminal having a receiver and method for removing known interferers from a digitized intermediate frequency signal |
| 05/03/2001 | WO2001031785A1 Pipelined programmable digital pulse delay |
| 05/03/2001 | US20010000661 Logic circuit utilizing capacitive coupling, an AD converter and a DA converter |
| 05/03/2001 | DE19948638C1 Signal flank correction circuit for video monitor compares difference value between sampled signal characteristic and its second differential with defined amplitude range for replacement by upper or lower limit value |
| 05/03/2001 | DE10053366A1 Input buffer circuit has amplifier circuit which is operated after elapse of preset time from reception of input signal from buffer |
| 05/02/2001 | EP1096683A1 Clock generator circuit |
| 05/02/2001 | EP1096679A2 Pulse width modulation for correcting non-uniformity of acoustic inkjet printhead |
| 05/02/2001 | EP1096678A1 Connection control circuit |
| 05/02/2001 | EP1096263A2 Jitter detector, phase difference detector and jitter detecting method |
| 05/02/2001 | EP1095451A1 Level shifting circuit arrangement and optical read/write device including the circuit arrangement |
| 05/02/2001 | EP1095284A2 Circuit for determining the time difference between two edges of a first and of a second digital signal |
| 05/02/2001 | EP0856167B1 Multi-stage current feedback amplifier |
| 05/02/2001 | CN1065349C Oscillating circuit and non-volatile semiconductor memory |
| 05/01/2001 | US6226344 Generation of a time period |
| 05/01/2001 | US6226324 Methods and systems for trimming a PWM signal |
| 05/01/2001 | US6226230 Timing signal generating apparatus and method |
| 05/01/2001 | US6226222 Synchronous semiconductor memory device having a function for controlling sense amplifiers |
| 05/01/2001 | US6225847 Complementary clock generator and method for generating complementary clocks |
| 05/01/2001 | US6225843 Semiconductor integrated circuit device |
| 05/01/2001 | US6225841 Semiconductor device using complementary clock and signal input state detection circuit used for the same |
| 05/01/2001 | US6225835 Amplifier free from duty-ratio error |
| 05/01/2001 | US6225832 Signal regeneration circuit |