Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass
Patents for H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass (25,714)
11/2002
11/28/2002US20020178391 High resolution clock signal generator
11/28/2002US20020177266 Selectable output edge rate control
11/28/2002US20020176299 High-speed zero phase restart of a multiphase clock
11/28/2002US20020175904 Driving circuit and display comprising the same
11/28/2002US20020175772 Power efficient delay stage for a voltage-controlled oscillator
11/28/2002US20020175730 Programmable differential delay circuit with fine delay adjustment
11/28/2002US20020175729 Differential CMOS controlled delay unit
11/28/2002US20020175728 Programmable differential delay circuit with fine delay adjustment
11/28/2002US20020175727 Ultra high speed clocked analog latch
11/28/2002US20020175724 Method and system for managing a pulse width of a signal pulse
11/28/2002US20020175718 Semiconductor integrated circuit device
11/28/2002US20020175715 Comparator and analog-to-digital converter
11/28/2002US20020175373 Semiconductor device
11/28/2002DE10123742A1 Regelung und Fehlerkorrektur für Impulsausgabe Control and error correction for pulse output
11/27/2002EP1261128A2 Comparator and analog-to-digital converter
11/27/2002EP1261127A2 Semiconductor integrated circuit device
11/27/2002EP1260899A2 Circuit and method for generating a delayed internal clock signal
11/27/2002EP1260822A2 Automatic test equipment for semiconductor device
11/27/2002EP1016086B1 Method and apparatus for adjusting the timing of signals over fine and coarse ranges
11/26/2002US6487673 Clock circuit and a computer system having said clock circuit
11/26/2002US6487141 Digital delay, digital phase shifter
11/26/2002US6486723 Programmable differential delay circuit with fine delay adjustment
11/26/2002US6486722 Semiconductor device including a control signal generation circuit allowing reduction in size
11/26/2002US6486716 Phase compensation circuit
11/26/2002US6486710 Differential voltage magnitude comparator
11/26/2002US6486705 Signal distribution scheme in field programmable gate array (FPGA) or field programmable system chip (FPSC) including cycle stealing units
11/26/2002US6486695 Protecting unit
11/21/2002WO2002093744A1 Apparatus/method for distributing a clock signal
11/21/2002US20020174374 High speed phase selector
11/21/2002US20020172314 Phase splitter using digital delay locked loops
11/21/2002US20020172299 Data width corrector
11/21/2002US20020172090 SDRAM having data latch circuit for outputting input data in synchronization with a plurality of control signals
11/21/2002US20020171496 Ring oscillator with adjustable delay
11/21/2002US20020171495 Oscillator averaging phase shift generator
11/21/2002US20020171465 Level shift circuit
11/21/2002US20020171453 Differential amplifier circuit capable of accurately amplifying even high-speeded signal of small amplitude
11/21/2002DE10150362A1 Phasenselektor hoher Geschwindigkeit Phase selector high speed
11/21/2002DE10122702A1 Producing second signal with clock based on second clock from first signal with first clock involves sampling first signal using second clock, phase shifted clock to detect defined logical state
11/21/2002DE10122023A1 Anordnung und Verfahren zur Ermittlung des jeweils aktuellen Pegels eines digitalen Signals Apparatus and method for determining the current level of a digital signal
11/20/2002EP1259038A2 Control and error correction for pulse generators
11/20/2002EP1258809A2 Programmable counters for setting arbitration delays
11/20/2002CN1094613C Interface circuit and method for low power loss transfer binary logic signals
11/19/2002US6483887 Timer control circuit
11/19/2002US6483757 Delay-locked loop with binary-coupled capacitor
11/19/2002US6483364 Ladder type clock network for reducing skew of clock signals
11/19/2002US6483362 Pulse generator
11/19/2002US6483360 Digital phase control using first and second delay lines
11/19/2002US6483359 Delay locked loop for use in semiconductor memory device
11/19/2002US6483342 Multi-master multi-slave system bus in a field programmable gate array (FPGA)
11/14/2002WO2002091577A2 Clock noise reduction method and apparatus
11/14/2002WO2002091471A2 Integrated circuit
11/14/2002US20020167857 Apparatus and method for distributing a clock signal on a large scale integrated circuit
11/14/2002US20020167363 Precision low jitter oscillator circuit
11/14/2002US20020167352 Method and apparatus for shifting the frequency spectrum of noise signals
11/14/2002US20020167349 Adjustable temperature-compensated threshold circuit with trip-points exceeding the given supplies
11/14/2002US20020167347 Phase-locked loop circuit
11/14/2002US20020167346 Circuits and methods for generating internal clock signal of intermediate phase relative to external clock
11/14/2002US20020167343 Pre-charged sample and hold
11/14/2002US20020167342 Signal reception circuit, data transfer control device and electronic equipment
11/14/2002US20020167341 Signal detection circuit, data transfer control device and electronic equipment
11/14/2002US20020167339 Data comparator using non-inverting and inverting strobe signals as a dynamic reference voltage and input buffer using the same
11/14/2002US20020167333 Differential signal output circuit
11/13/2002EP1257058A2 Device and method for determining the present logic level of a digital signal
11/13/2002CN1379427A Time delay circuit
11/12/2002US6480426 Semiconductor integrated circuit device
11/12/2002US6480311 Peak-hold circuit and an infrared communication device provided with such a circuit
11/12/2002US6480134 Analog-to-digital converter with a power saving capability
11/12/2002US6480048 Circuit for generating an inverse signal of a digital signal with a minimal delay difference between the inverse signal and the digital signal
11/12/2002US6480045 Digital frequency multiplier
11/12/2002US6480035 Phase detector with minimized phase detection error
11/12/2002US6480026 Multi-functional I/O buffers in a field programmable gate array (FPGA)
11/12/2002US6480024 Circuit configuration for programming a delay in a signal path
11/12/2002CA2199902C Interface circuit and method for transmitting binary logic signals with reduced power dissipation
11/07/2002US20020166003 Method and apparatus for a failure-free synchronizer
11/07/2002US20020163986 Method and apparatus for generating a phase dependent control signal
11/07/2002US20020163958 Apparatus for and method of measuring jitter
11/07/2002US20020163836 Semiconductor device
11/07/2002US20020163380 Integrated circuit
11/07/2002US20020163367 Clock supply bias circuit and single-phase clock drive frequency dividing circuit using the same
11/06/2002CN1093995C Fast sigma-delta modulator having controlled clock generator
11/06/2002CN1093994C Wireless digital communication device, and pulse shaping network
11/05/2002US6476789 System construction of semiconductor devices and liquid crystal display device module using the same
11/05/2002US6476744 Method and apparatus for generating pulses from analog waveforms
11/05/2002US6476659 Voltage level shifter and phase splitter
11/05/2002US6476657 Pulse generator for generating an output in response to a delay time
11/05/2002US6476655 Semiconductor device
11/05/2002US6476654 Slew rate adjusting circuit
11/05/2002US6476653 DLL circuit adjustable with external load
11/05/2002US6476652 Delay locked loop for use in synchronous dynamic random access memory
11/05/2002US6476646 Sense amplifier of semiconductor integrated circuit
11/05/2002US6476640 Method for buffering an input signal
10/2002
10/31/2002US20020158671 Fast locking phase frequency detector
10/31/2002DE10162243A1 Zeitgebersteuerschaltung Timing control circuit
10/31/2002DE10146080A1 Driver circuit for matching clock signal phase e.g. in memory circuits has four series-connected transistors and two control inputs
10/31/2002DE10119051A1 Schaltungsanordnung zur Freigabe eines Taktsignals in Abhängigkeit von einem Freigabesignal Circuit arrangement for the release of a clock signal in response to an enable signal
10/30/2002EP1253716A2 Delay circuit and oscillator circuit using the same
10/30/2002CN1377519A Method and apparatus for automatically compensating spread spectrum clock generator
10/29/2002US6473865 Apparatus comprising clock control circuit, method of controlling clock signal and device using internal clock signal synchronized to external clock signal
10/29/2002US6473455 Method for compensating a phase delay of a clock signal
10/29/2002US6473316 Phase control circuit and switching regulator
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