Patents
Patents for H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass (25,714)
08/2002
08/27/2002US6441670 5V-tolerant receiver for low voltage CMOS technologies
08/27/2002US6441666 System and method for generating clock signals
08/27/2002US6441665 Semiconductor integrated circuit
08/27/2002US6441662 DLL circuit that can prevent erroneous operation
08/27/2002US6441659 Frequency-doubling delay locked loop
08/27/2002US6441657 Combinational delay circuit for a digital frequency multiplier
08/27/2002US6441656 Clock divider for analysis of all clock edges
08/27/2002US6441650 Offset comparator and method for forming same
08/27/2002US6441649 Rail-to-rail input clocked amplifier
08/27/2002US6441596 Switching regulator with reduced high-frequency noise
08/27/2002US6439679 Pulse with modulation signal generating methods and apparatuses
08/22/2002WO2002065687A1 Direct digital synthesizer based on delay line with sorted taps
08/22/2002US20020114406 Signal processing circuit and method for measuring pulse width under existence of chattering noise
08/22/2002US20020113643 Circuit for the filtering of parasitic logic signals
08/22/2002US20020113637 Phase-interpolation circuit and a phase-interpolation signal generating device applying the same
08/22/2002US20020113633 Method and apparatus for process independent clock signal distribution
08/22/2002US20020113630 Edge multiplier circuit
08/22/2002US20020113627 Input buffer circuit capable of suppressing fluctuation in output signal and reducing power consumption
08/22/2002US20020113626 Differential line driver having adjustable common mode operation
08/21/2002EP1232566A1 Method and apparatus for correcting imperfectly equalized bipolar signals
08/20/2002US6438163 Cable length and quality indicator
08/20/2002US6438162 Implementation method for adaptive equalizer in CMOS
08/20/2002US6438067 Clock generating circuit ensuring a wide lock-allowing frequency range and allowing reduction in layout area as well as a semiconductor device provided with the same
08/20/2002US6438034 Semiconductor device
08/20/2002US6437713 Programmable logic device having amplitude and phase modulation communication
08/20/2002US6437620 Circuit and method for multi-phase alignment
08/20/2002US6437619 Clock generation circuit, control method of clock generation circuit, clock reproducing circuit, semiconductor memory device, and dynamic random access memory
08/20/2002US6437617 Method of controlling a clock signal and circuit for controlling a clock signal
08/20/2002US6437613 Clock generating circuit for compensation of delay difference using closed loop analog synchronous mirror delay structure
08/20/2002US6437607 Non linear circuit for open load control in low-side driver type circuits
08/20/2002US6437553 Method for delay line linearity testing
08/15/2002WO2002035756A3 Active continuous-time filter with increased dynamic range in the presence of blocker signals
08/15/2002US20020112194 Clock phase generator
08/15/2002US20020110211 Direct digital synthesizer based on delay line with sorted taps
08/15/2002US20020109538 Semiconductor device including a control signal generation circuit allowing reduction in size
08/15/2002US20020109533 Automatic frequency rate switch
08/15/2002US20020109532 Comparator circuit
08/15/2002US20020109075 DC offset cancellation circuit, differential amplification circuit with DC offset cancellation circuit, photo-electric pulse conversion circuit, pulse shaping circuit, and pulse generation circuit
08/14/2002EP1231749A1 Data slicer and RF receiver employing the same
08/14/2002EP1230734A1 Adaptive dead time control for push-pull switching circuits
08/14/2002EP0865683B1 Serial multi-gb/s data receiver
08/13/2002US6434062 Delay locked loop for use in semiconductor memory device
08/13/2002US6433711 System and method for offset error compensation in comparators
08/13/2002US6433627 GTL+one-one/zero-zero detector
08/13/2002US6433622 Voltage stabilized low level driver
08/13/2002US6433619 Pump circuit boosting a supply voltage
08/13/2002US6433614 MOSFET-based switch
08/13/2002US6433611 Voltage level shifting circuit
08/13/2002US6433610 Current clamp circuit
08/13/2002US6433609 Double-gate low power SOI active clamp network for single power supply and multiple power supply applications
08/13/2002US6433606 Clock driver circuit and method of routing clock interconnections
08/13/2002US6433605 Low wiring skew clock network with current mode buffer
08/13/2002US6433600 Method and apparatus for glitch protection for input buffers in a source-synchronous environment
08/13/2002US6433582 Voltage level shifter circuit
08/08/2002WO2002015401A3 Voltage stabilized low level driver
08/08/2002US20020106038 Data Slicer and RF receiver employing the same
08/08/2002US20020105838 Synchronous semiconductor memory device performing data output in synchronization with external clock
08/08/2002US20020105367 Phase adjustor for semiconductor integrated circuit device
08/08/2002US20020105364 Line driver for supplying symmetrical output signals to a two-wire communication bus
08/08/2002US20020105363 Current comparator
08/08/2002DE10200698A1 Genaues Zeitverzögerungssystem und Verfahren unter Verwendung eines ungenauen Oszillators Exact time delay system and method using an inaccurate oscillator
08/07/2002EP1229646A2 Two step variable length delay circuit
08/07/2002EP1228632A2 Phase detector and lock detector for a pll
08/06/2002US6429734 Differential active loop filter for phase locked loop circuits
08/06/2002US6429722 Clock noise reduction method
08/06/2002US6429717 Receiving circuit
08/06/2002US6429702 CMOS buffer for driving a large capacitive load
08/06/2002US6429698 Clock multiplexer circuit with glitchless switching
08/06/2002US6429697 Multi-stage, low-offset, fast-recovery, comparator system and method
08/06/2002US6429695 Differential comparison circuit
08/06/2002US6429694 Apparatus and method in an integrated circuit for delay line phase difference amplification
08/06/2002US6429693 Digital fractional phase detector
08/06/2002US6429687 Semiconductor integrated circuit device
08/01/2002WO2002060059A2 Method and circuit for maintaining a single stable dc operating point
08/01/2002WO2002003551A3 Digital delay element
08/01/2002US20020103618 System and method for delay line testing
08/01/2002US20020101947 Sampling clock generator circuit and data receiver using the same
08/01/2002US20020101885 Jitter buffer and methods for control of same
08/01/2002US20020101744 Charge pump power supply
08/01/2002US20020101271 Two step variable length delay circuit
08/01/2002US20020101270 Current pulse receiving circuit
08/01/2002US20020100954 Circuit for generating an asynchronous signal pulse
08/01/2002US20020100883 Method and apparatus for a phototransistor pulse width converter
08/01/2002DE10157006A1 Hochgeschwindigkeitssignalfenstererfassung High-speed signal acquisition window
08/01/2002DE10148515A1 Frequenzspannungswandler Frequency voltage converter
07/2002
07/31/2002EP1227587A1 Apparatus and method for obtaining stable delays for clock signals
07/31/2002EP1010053B1 Interface circuit for full-custom and semi-custom timing domains
07/30/2002US6426900 Synchronous semiconductor memory device performing data output in synchronization with external clock
07/30/2002US6426662 Twisted-ring oscillator and delay line generating multiple phases using differential dividers and comparators to match delays
07/30/2002US6426661 Clock distribution with constant delay clock buffer circuit
07/30/2002US6426660 Duty-cycle correction circuit
07/30/2002CA2251378C High-speed and high-precision phase locked loop
07/25/2002WO2002057927A2 Input/output cell with a programmable delay element
07/25/2002US20020099969 Data input and output device using timer function
07/25/2002US20020097592 Frequency voltage converter
07/25/2002US20020097212 Display device having an improved voltage level converter circuit
07/25/2002US20020097075 Clock signal correction circuit and semiconductor device implementing the same
07/25/2002US20020097074 Synchronous semiconductor device for adjusting phase offset in a delay locked loop
07/25/2002DE10200859A1 System und Verfahren zum Steuern von Verzögerungszeiten bei Floating-Body-Cmosfet-Invertern System and method for controlling delay times for floating body CMOSFET inverters
07/25/2002DE10065376C1 Verzögerungsschaltung mit einstellbarer Verzögerung Delay circuit with adjustable delay