Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass
Patents for H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass (25,714)
05/2003
05/06/2003US6559697 Multiplied clock generating circuit
05/06/2003US6559694 Timing signal occurrence circuit
05/06/2003US6559688 Voltage comparing circuit
05/06/2003US6559687 Rail-to-rail CMOS comparator
05/06/2003US6559686 Analog envelope detector
05/06/2003US6559682 Dual-mixer loss of signal detection circuit
05/06/2003US6559679 Glitch free clock multiplexer circuit and method thereof
05/02/2003EP1305880A2 5-ary receiver utilizing common mode insensitive differential offset comparator
05/02/2003EP1133728B1 Clock generation and distribution in an emulation system
05/02/2003EP0843417B1 Phase locked loop circuit
05/01/2003WO2003036314A1 Timing generator, semiconductor testing device, and timing generating method
05/01/2003US20030081473 System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal
05/01/2003US20030081472 System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal
05/01/2003US20030080892 Chopper analog-to-digital converter
05/01/2003US20030080800 Integrated analog multiplexer
05/01/2003US20030080799 Fast mono-cycle generating circuit using full rail swing logic circuits
05/01/2003US20030080796 Signal level shift circuit
05/01/2003US20030080794 Device and method for clock generation
05/01/2003US20030080793 Flip-flops and clock generators that utilize differential signals to achieve reduced setup times and clock latency
05/01/2003US20030080792 Systems and methods for minimizing harmonic interference
05/01/2003US20030080789 Bus control circuit
05/01/2003US20030080785 Receiver apparatus and method of propagating a signal
05/01/2003US20030080784 Comparing circuit, comparator, level determining circuit and threshold voltage setting method
05/01/2003US20030080783 Pulse processing circuit and frequency multiplier circuit
04/2003
04/29/2003US6557152 Method of designing signal distribution circuit and system for supporting the same
04/29/2003US6556643 Majority filter counter circuit
04/29/2003US6556160 Circuit for converting an analog signal to a PWM signal
04/29/2003US6556089 Electronic circuitry
04/29/2003US6556072 Low distortion circuit with switched capacitors
04/29/2003US6556050 High speed signal window detection
04/29/2003CA2280755C Regulating dead time given varying pulse repetition rates
04/24/2003WO2003034592A1 Adaptive level binary logic
04/24/2003WO2003034589A2 Digital level shifter with reduced power dissipation and false transmission blocking
04/24/2003WO2002056474A3 Clock interpolation through capacitive weighting
04/24/2003US20030078767 Method and system for implementing a low complexity spectrum estimation technique for comfort noise generation
04/24/2003US20030076182 Chattering eliminating apparatus including oscillation circuit using charging and discharging operations
04/24/2003US20030076147 Method and apparatus for generating a clock signal
04/24/2003US20030076145 Compact delay circuit for cmos integrated circuits used in low voltage low power devices
04/24/2003US20030076144 Schmitt trigger circuit consuming low power
04/24/2003US20030076143 Semiconductor device, semiconductor system, and digital delay circuit
04/24/2003US20030076142 Delay locked loop with multi-phases
04/24/2003US20030076136 Monocycle generator
04/24/2003US20030076134 Data receiver and data receiving method using signal integration
04/24/2003US20030075180 Mask assembly
04/23/2003EP1304801A1 PECL buffer
04/23/2003EP1303914A1 Circuit for generating an inverse signal of a digital signal with a minimal delay difference between the inverse signal and the digital signal
04/23/2003EP1303911A1 Switching control circuit
04/23/2003CN1413387A Communication terminal having receiver and method for removing known interferers from digitized intermediate frequency signal
04/23/2003CN1412947A Buffer capable of regulating work period and its operation method
04/23/2003CN1412946A Reversed polarity induction electric energy generation circuit of pulse power supply
04/23/2003CN1412639A Apparatus for generating clock signal
04/23/2003CN1412636A Pulse processing circuit and frequency multiplier circuit
04/22/2003US6553088 Digital delay phase locked loop
04/22/2003US6552957 Semiconductor integrated circuit having a signal receiving circuit
04/22/2003US6552595 Current-controlled high voltage discharge scheme
04/22/2003US6552589 Method and apparatus for process independent clock signal distribution
04/22/2003US6552587 Synchronous semiconductor device for adjusting phase offset in a delay locked loop
04/22/2003US6552584 Output stage for high-speed comparator circuits
04/22/2003US6552578 Power down circuit detecting duty cycle of input signal
04/22/2003US6552570 Input circuit with non-delayed time blanking
04/17/2003WO2003032491A1 Reduction of ringing and inter-symbol interference in optical communications
04/17/2003WO2002048727A3 Calibrating single ended channels for obtaining differential performance level
04/17/2003US20030074609 System and method for automatic deskew across a high speed, parallel interconnection
04/17/2003US20030072400 Programmable feedback delay phase-locked loop for high-speed input/output timing budget management and method of operation thereof
04/17/2003US20030072399 Apparatus for signaling that a predetermined time value has elapsed
04/17/2003US20030072332 Intelligent delay insertion based on transition
04/17/2003US20030071691 Multi-mode VCO
04/17/2003US20030071665 Frequency multiplying system having a plurality of output frequencies
04/17/2003US20030071659 Low voltage comparator
04/17/2003US20030071655 Digital level shifter with reduced power dissipation and false transmission blocking
04/17/2003DE10161347C1 Clock signal conversion circuit used with phase-locked loop circuit has 2 difference amplifiers each converting input clock signal pair into unsymmetrical clock signals
04/17/2003DE10018190C2 Unterbrechnungsloses Umschalten zwischen zwei Oszillator-Präzisionstaktgebern Interruption Separate switching between two oscillator precision clocks
04/16/2003EP1303043A1 Digital filter for suppressing glitches
04/16/2003EP1302837A1 Clock signal generation apparatus
04/16/2003EP1302039A2 Decoding of asynchronous data signals, using calculation of derivatives
04/16/2003EP1031203A4 Delay locked loop circuitry for clock delay adjustment
04/16/2003EP0855103B1 Peak detector and use thereof
04/16/2003CN1411651A Single chip CMOS transmitter/receiver and method of using same
04/15/2003US6549605 Limiting loss in a circuit
04/15/2003US6549054 DC offset cancellation circuit, differential amplification circuit with DC offset cancellation circuit, photo-electric pulse conversion circuit, pulse shaping circuit, and pulse generation circuit
04/15/2003US6549053 Adjustable offset voltage circuit
04/15/2003US6549052 Variable delay circuit
04/15/2003US6549047 Variable delay circuit and semiconductor integrated circuit device
04/15/2003US6549045 Circuit for providing clock signals with low skew
04/15/2003US6549039 Hi gain clock circuit
04/10/2003WO2003030368A1 Compensating for differences between clock signals
04/10/2003WO2002091577A8 Clock noise reduction method and apparatus
04/10/2003WO2002054598A3 Precision phase generator
04/10/2003US20030069041 Device for generating a clock signal
04/10/2003US20030067975 Signal processor having feedback loop control for decision feedback equalizer
04/10/2003US20030067973 Block interpolation filter structure using lookup table
04/10/2003US20030067642 Ringing and inter-symbol interference reduction in optical communications
04/10/2003US20030067338 Digitally controllable internal clock generating circuit of semiconductor memory device and method for same
04/10/2003US20030067333 Digital phase control using first and second delay lines
04/10/2003US20030067323 Signal converting system having level converter for use in high speed semiconductor device and method therefor
04/10/2003CA2457499A1 Compensating for differences between clock signals
04/09/2003EP1300948A2 High speed peak amplitude comparator
04/09/2003EP0843846B1 Clock signal distribution and synchronisation in a digital system
04/09/2003EP0653793B1 Semiconductor device
04/09/2003CN2544466Y No sudden wave interfefence clock pulse output circuit
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