| Patents for H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass (25,714) |
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| 07/17/2004 | CA2455276A1 Physical layers |
| 07/15/2004 | WO2004059845A2 Clock signal generator having a differential output |
| 07/15/2004 | WO2004059839A1 Circuit arrangement |
| 07/15/2004 | WO2004036734A3 Pulse generator |
| 07/15/2004 | US20040136255 Current integrating sense amplifier for memory modules in RFID |
| 07/15/2004 | US20040136239 Semiconductor integrated circuit device with erasable and programmable fuse memory |
| 07/15/2004 | US20040135760 Display device having an improved voltage level converter circuit |
| 07/15/2004 | US20040135615 Clock divider circuit |
| 07/15/2004 | US20040135614 System and method for generating two effective frequencies using a single clock |
| 07/15/2004 | US20040135613 Pulse clock/signal delay apparatus and method |
| 07/15/2004 | US20040135612 Delayed tap signal generating circuit for controlling delay by interpolating two input clocks |
| 07/15/2004 | US20040135610 Method and apparatus to delay signal latching |
| 07/15/2004 | US20040135608 Variable duty cycle clock generation circuits and methods and systems using the same |
| 07/15/2004 | US20040135607 Clock frequency multiplier |
| 07/15/2004 | US20040135606 Circuit and method for inducing jitter to a signal |
| 07/15/2004 | US20040135604 Delay locked loops having blocking circuits therein that enhance phase jitter immunity and methods of operating same |
| 07/15/2004 | US20040135601 Clock multiplier circuit |
| 07/15/2004 | US20040135598 Input circuit |
| 07/14/2004 | EP1437830A1 Semiconductor integrated circuit |
| 07/14/2004 | EP1437661A2 Integrated circuit device, semiconductor memory, and integrated circuit system coping with high-frequency clock signal |
| 07/14/2004 | EP1436958A1 A digital implementation of multi-channel demodulators |
| 07/14/2004 | EP1142115B1 A method and apparatus for reducing signal transmission delay using skewed gates |
| 07/14/2004 | CN1512672A Digital signal generator |
| 07/14/2004 | CN1512669A Pulse width modulation type current regulator |
| 07/14/2004 | CN1512668A Flow-clamping square pulse signal source for biological film |
| 07/14/2004 | CN1512667A Co-phased multiple period signal generator |
| 07/13/2004 | US6763475 System for controlling the effects of glitching using level sensitive latches |
| 07/13/2004 | US6763079 Semiconductor device allowing easy confirmation of operation of built in clock generation circuit |
| 07/13/2004 | US6763063 Peak value estimation of sampled signal |
| 07/13/2004 | US6762636 Circuit and method for adjusting duty cycle of a high speed, low swing output signal |
| 07/13/2004 | US6762633 Delay locked loop circuit with improved jitter performance |
| 07/13/2004 | US6762632 Reset driver circuits and methods |
| 07/13/2004 | US6762630 Integrated circuit having a synchronous and an asynchronous circuit and method for operating such an integrated circuit |
| 07/13/2004 | US6762628 Method for operating a comparator and a pre-amplifier of an integrated circuit, which pre-amplifier is connected in series to the comparator, as well as an integrated circuit arrangement comprising a comparator and a pre-amplifier which is connected in series to the comparator |
| 07/08/2004 | WO2004057760A1 Shift resistor and method for driving same |
| 07/08/2004 | WO2004038918A3 Method and device for generating a clock signal with predetermined clock signal properties |
| 07/08/2004 | US20040130962 Delayed locked loop implementation in a synchronous dynamic random access memory |
| 07/08/2004 | US20040130469 Decision feedback equalization employing a lookup table |
| 07/08/2004 | US20040130373 Low-swing impedance controlled unity gain differential clock driver |
| 07/08/2004 | US20040130372 Semiconductor apparatus |
| 07/08/2004 | US20040130365 High resolution interleaved delay chain |
| 07/08/2004 | US20040130363 Storing an unchanging binary code in an integrated circuit |
| 07/08/2004 | US20040130359 Current sensing circuit and method of a high-speed driving stage |
| 07/08/2004 | US20040130356 Sampling/holding method and circuit |
| 07/08/2004 | US20040130355 High-voltage detecting circuit |
| 07/08/2004 | DE19510055B4 Schaltungsanordnung zum Auswerten eines binären, durch Stromschwellenwerte definierten Signals Circuit arrangement for evaluating a binary signal defined by current thresholds |
| 07/08/2004 | DE10240134B4 Verfahren und Vorrichtung zum Auftakten zeitdiskreter Signale Method and apparatus for time-discrete signals preludes |
| 07/08/2004 | DE10227839B4 Phasendifferenzerfassungsschaltung Phase difference detecting circuit |
| 07/07/2004 | EP1435689A1 Method and circuitry for reducing the skew between two signals |
| 07/07/2004 | CN1156975C Clock generation circuit, Serial/parallel converter and parallel/serial converter |
| 07/06/2004 | US6760855 System and method for reducing a ground bounce during write by selectively delaying address and data lines with different multiple predetermined amount of delay |
| 07/06/2004 | US6760803 Aligning and offsetting bus signals |
| 07/06/2004 | US6760675 Adjustable high current and high voltage pulse generator |
| 07/06/2004 | US6760371 Method and apparatus implementation of a zero forcing equalizer |
| 07/06/2004 | US6760261 DQS postamble noise suppression by forcing a minimum pulse length |
| 07/06/2004 | US6759974 Encoder and decoder for data transfer in superconductor circuits |
| 07/06/2004 | US6759911 Delay-locked loop circuit and method using a ring oscillator and counter-based delay |
| 07/06/2004 | US6759886 Clock generating circuit generating a plurality of clock signals |
| 07/06/2004 | US6759885 Self-calibrating clock generator for generating process and temperature independent clock signals |
| 07/06/2004 | US6759882 System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal |
| 07/06/2004 | US6759878 Voltage comparator circuit and substrate bias adjusting circuit using same |
| 07/01/2004 | WO2004055989A2 Low lock time delay locked loops using time cycle supppressor |
| 07/01/2004 | WO2004055988A2 Coarse delay tuner circuits with edge suppressors in delay locked loops |
| 07/01/2004 | WO2004055964A1 Digital programmable pulse modulator with digital frequency control |
| 07/01/2004 | WO2004032199A3 Constant delay zero standby differential logic receiver and method |
| 07/01/2004 | US20040125930 Identification of an integrated circuit from its physical manufacture parameters |
| 07/01/2004 | US20040125902 Phase shifter, phase shifting method and skew compensation system for high-speed parallel signaling |
| 07/01/2004 | US20040125119 Methods and apparatuses for filtering pulses |
| 07/01/2004 | US20040124929 Frequency detector detecting variation in frequency difference between data signal and clock signal |
| 07/01/2004 | US20040124918 Wideband common-mode regulation circuit |
| 07/01/2004 | US20040124905 Circuit configuration for signal balancing in antiphase bus drivers |
| 07/01/2004 | US20040124900 Digital signal delay device |
| 07/01/2004 | US20040124899 Synchronizer with zero metastability |
| 07/01/2004 | US20040124897 Digital control logic circuit having a characteristic of time hysteresis |
| 07/01/2004 | US20040124892 Use of analog-valued floating-gate transistors to match the electrical characteristics of interleaved and pipelined circuits |
| 07/01/2004 | US20040124891 Method and amplification circuit with pre-emphasis |
| 07/01/2004 | US20040124885 Peak detection circuit with double peak detection stages |
| 07/01/2004 | US20040124715 Apparatus and method for resonance reduction |
| 07/01/2004 | DE4327116B4 Programmierbare Verzögerungsschaltung Programmable delay circuit |
| 07/01/2004 | DE10260722A1 Arrangement for balancing a delay chain, especially for a motor vehicle radar system, has a delay chain or line with individual delay members and associated voltage taps that are connected to a multiplexer and counter |
| 06/30/2004 | EP1434348A1 Wideband common-mode regulation circuit |
| 06/30/2004 | EP1433059A2 Clock loss detection and switchover circuit |
| 06/30/2004 | CN2622710Y Digital indicator for duty ratio of pulse power output voltage |
| 06/30/2004 | CN1509518A Apparatus/method for distributing clock signal |
| 06/30/2004 | CN1508929A Live-line plugging control circuit for pluggable module and control method thereof |
| 06/30/2004 | CN1156078C Electric circuit device for generating intercompensative signals |
| 06/30/2004 | CN1156076C Delay circuit device |
| 06/29/2004 | US6757327 Serial data communication receiver having adaptive termination resistors |
| 06/29/2004 | US6756841 Variable offset amplifier circuits and their applications |
| 06/29/2004 | US6756834 Direct power-to-ground ESD protection with an electrostatic common-discharge line |
| 06/29/2004 | US6756833 Delayed signal generation circuit |
| 06/29/2004 | US6756832 Digitally-programmable delay line for multi-phase clock generator |
| 06/29/2004 | US6756827 Clock multiplier using masked control of clock pulses |
| 06/29/2004 | US6756822 Phase detector employing asynchronous level-mode sequential circuitry |
| 06/29/2004 | US6756819 Synchronization circuit |
| 06/29/2004 | US6756818 Voltage-controlled delay line with reduced timing errors and jitters |
| 06/29/2004 | US6756808 Clock edge detection circuit |
| 06/29/2004 | US6756775 Quasi-periodic optical sampling |
| 06/29/2004 | US6756699 Device and method for calibrating the pulse duration of a signal source |
| 06/29/2004 | CA2170764C High speed differential receiver for data communications |