| Patents for H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass (25,714) |
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| 09/02/2004 | WO2004074991A2 Low power, area-efficient circuit to provide clock synchronization |
| 09/02/2004 | WO2004014066A3 Method and devic the for setting the slice level in a binary signal |
| 09/02/2004 | US20040169551 Active filter circuit with dynamically modifiable gain |
| 09/02/2004 | US20040169539 Miller effect compensation technique for DLL phase interpolator design |
| 09/02/2004 | US20040169538 DLL circuit |
| 09/02/2004 | US20040169535 Semiconductor integrated circuit device |
| 09/02/2004 | US20040169528 Pulse peak and/or trough detector |
| 09/02/2004 | DE10335069A1 Synchrone Halbleiterspeichervorrichtung, die ein Einstellen des Datenausgabezeitablaufs ermöglicht The synchronous semiconductor memory device which allows adjusting the data output timing |
| 09/02/2004 | DE10230116B4 Verfahren und Vorrichtung für ein digitales Logikeingangssignalrauschfilter Method and apparatus for a digital logic input signal noise filter |
| 09/01/2004 | EP1453203A1 Miller effect compensation for a DLL phase interpolator |
| 09/01/2004 | EP1453202A1 Nyquist pulse driver for data transmission |
| 09/01/2004 | EP1451930A2 Digitally controlled pulse width adjusting circuit |
| 09/01/2004 | EP1451666A2 Glitch free clock selection switch |
| 09/01/2004 | EP1451598A2 Test machine for testing an integrated circuit with a comparator |
| 09/01/2004 | CN2638332Y Cross time clock domain signal synchronous treatment circuit |
| 09/01/2004 | CN1165110C Digital frequency monitoring |
| 08/31/2004 | US6784717 Input buffer system using low voltage transistors |
| 08/31/2004 | US6784716 Clock generation circuit and clock conversion circuit |
| 08/31/2004 | US6784714 Digital phase control using first and second delay lines |
| 08/31/2004 | US6784710 Multistage pulse width modulator |
| 08/31/2004 | US6784709 Clock generator to control a pules width according to input voltage level in semiconductor memory device |
| 08/31/2004 | US6784708 Slew rate sensing and control of a high-voltage output driver for a variable voltage range and variable output load |
| 08/31/2004 | US6784707 Delay locked loop clock generator |
| 08/31/2004 | US6784701 CMOS buffer circuit |
| 08/31/2004 | US6784699 Glitch free clock multiplexing circuit with asynchronous switch control and minimum switch over time |
| 08/31/2004 | US6784689 Transmission gate based signal transition accelerator |
| 08/26/2004 | WO2004073293A2 40-gb/s clock and data recovery circuit in 0.18 micrometers technology |
| 08/26/2004 | WO2004073175A2 Adaptive input logic for phase adjustments |
| 08/26/2004 | US20040165671 Nyquist pulse driver for data transmission |
| 08/26/2004 | US20040165449 Method and circuit for generating constant slew rate output signal |
| 08/26/2004 | US20040164781 Low power, area-efficient circuit to provide clock synchronization |
| 08/26/2004 | US20040164779 Circuit for programmable stepless clock shifting |
| 08/26/2004 | US20040164777 Comparator |
| 08/26/2004 | US20040164744 Abnormality detection apparatus of comparator |
| 08/26/2004 | DE10348327A1 Systeme und Verfahren zum Einbringen von Test-Jitter in Daten-Bit-Ströme Systems and methods for inserting test jitter in data bit streams |
| 08/26/2004 | DE102004005681A1 Selbstausrichtungssystem für Komplementtakte Self-alignment system for Komplementtakte |
| 08/25/2004 | EP1450238A1 Circuit for programmable stepless clock shifting |
| 08/25/2004 | EP1449302A1 Asynchronous sequencer circuit with flexibly ordered output signal edges |
| 08/25/2004 | EP1145431B1 Electronic circuitry |
| 08/25/2004 | CN1524333A Electronic control systems and methods |
| 08/25/2004 | CN1523758A Noise wiping circuit |
| 08/25/2004 | CN1523669A 开关电路装置 Switch circuit device |
| 08/25/2004 | CN1523609A Synchronous semiconductor memory device allowing adjustment of data output timing |
| 08/25/2004 | CN1164034C Synchronous delay circuit device |
| 08/24/2004 | US6782046 Decision-directed adaptation for coded modulation |
| 08/24/2004 | US6781905 Serial data detection circuit performing same offset adjustment to signal receiver as performed to reference receiver |
| 08/24/2004 | US6781470 Tunable oscillator |
| 08/24/2004 | US6781442 Self-bias adjustment circuit |
| 08/24/2004 | US6781438 Method and device for generating a reference voltage |
| 08/24/2004 | US6781426 Nanosecond monolithic CMOS readout cell |
| 08/24/2004 | US6781419 Method and system for controlling the duty cycle of a clock signal |
| 08/19/2004 | WO2004070987A2 Analog floating gate voltage sense during dual conduction programming |
| 08/19/2004 | WO2004070937A2 System and method for calibrating the clock frequency of a clock generator unit over a data line |
| 08/19/2004 | WO2004070406A1 Detection device, detection method, and program |
| 08/19/2004 | US20040160833 Synchronous semiconductor memory device allowing adjustment of data output timing |
| 08/19/2004 | US20040160344 Robust system for transmitting and receiving map data |
| 08/19/2004 | US20040160265 Mixer system |
| 08/19/2004 | US20040160257 Latch-based pulse generator |
| 08/19/2004 | US20040160255 Semiconductor circuit |
| 08/19/2004 | US20040160254 Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof |
| 08/19/2004 | US20040160253 Self alignment system for complement clocks |
| 08/19/2004 | US20040160252 Circuit arrangement and method for producing a pulse width modulated signal |
| 08/19/2004 | US20040160251 High density magnetic RAM and array architecture using a one transistor, one diode, and one MTJ cell |
| 08/19/2004 | US20040160250 Analog delay locked loop with tracking analog-digital converter |
| 08/19/2004 | US20040160245 Linear low noise transconductance cell |
| 08/19/2004 | US20040160243 System, method and apparatus for improving sense amplifier performance characteristics using process feedback |
| 08/19/2004 | US20040159896 Semiconductor integrated circuit device |
| 08/19/2004 | DE19653160B4 Digitale Laufzeitverriegelungsschleifenschaltung, die eine synchrone Verzögerungsleitung verwendet Digital delay locked loop circuit using a synchronous delay line |
| 08/18/2004 | EP1374242B1 Storing an unchanging binary code in an integrated circuit |
| 08/18/2004 | EP1355427A9 Differential comparator circuit |
| 08/18/2004 | EP1188239B1 Dual control analog delay element |
| 08/18/2004 | CN1521951A Synchronization circuit and synchronization method |
| 08/18/2004 | CN1521947A Multi-signal sorting method for realizing multi-stop TDC function |
| 08/17/2004 | US6779124 Selectively deactivating a first control loop in a dual control loop circuit during data transmission |
| 08/17/2004 | US6778618 Methods and devices for minimizing interblock interference in discrete multi-tone devices |
| 08/17/2004 | US6778418 Power-supply voltage frequency control circuit |
| 08/17/2004 | US6778111 Multi-dimensional deglitch filter for high speed digital signals |
| 08/17/2004 | US6778033 Voltage control for clock generating circuit |
| 08/17/2004 | US6778002 Semiconductor integrated circuit device including a substrate bias controller and a current limiting circuit |
| 08/17/2004 | US6778000 Integrated circuit devices that provide constant time delays irrespective of temperature variation |
| 08/17/2004 | US6777996 Radio frequency clamping circuit |
| 08/17/2004 | US6777995 Interlaced delay-locked loops for controlling memory-circuit timing |
| 08/17/2004 | US6777994 Clock generator |
| 08/17/2004 | US6777993 Method and apparatus for adjusting the phase and frequency of a periodic wave |
| 08/17/2004 | US6777987 Signal buffer for high-speed signal transmission and signal line driving circuit including the same |
| 08/17/2004 | US6777983 Differential voltage transmission circuit |
| 08/12/2004 | WO2004068711A2 Comparator and method for operating the comparator |
| 08/12/2004 | WO2004068706A2 Programmable dual-edge triggered counter |
| 08/12/2004 | WO2002084871A3 Method and apparatus for generatng pulses from analog waveforms |
| 08/12/2004 | US20040158757 Interleaved delay line for phase locked and delay locked loops |
| 08/12/2004 | US20040156432 Processing a received signal at a detection circuit |
| 08/12/2004 | US20040156429 Systems and methods for injection of test jitter in data bit-streams |
| 08/12/2004 | US20040155709 Operational amplification circuit, overheat detecting circuit and comparison circuit |
| 08/12/2004 | US20040155693 Level shifter having automatic delay adjusting function |
| 08/12/2004 | US20040155690 Adaptive input logic for phase adjustments |
| 08/12/2004 | US20040155688 Pulse generating circuit |
| 08/12/2004 | US20040155687 40-Gb/s clock and data recovery circuit in 0.18mum technology |
| 08/12/2004 | US20040155686 Analog delay locked loop having duty cycle correction circuit |
| 08/12/2004 | US20040155682 High-speed cross-coupled sense amplifier |
| 08/12/2004 | DE10303248A1 Signal delay device has register for temporary storage of sampled value(s) of input signal in parallel with memory device; output of temporary storage device is connected to interpolation device |