Patents
Patents for H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass (25,714)
03/2004
03/16/2004US6708238 Input/output cell with a programmable delay element
03/16/2004US6707866 Clock generator, clock generating method, and signal receiver
03/16/2004US6707410 Digital pixel sensor with a dynamic comparator having reduced threshold voltage sensitivity
03/16/2004US6707408 Sigma-delta pulse-width-modulated signal generator circuit
03/16/2004US6707405 Integrated analog multiplexer
03/16/2004US6707332 Clock generating circuit and method thereof
03/16/2004US6707331 High speed one-shot circuit with optional correction for process shift
03/16/2004US6707330 Semiconductor device having internal circuit operating in synchronization with internal clock signal
03/16/2004US6707320 Clock detect indicator
03/16/2004US6707319 Frequency comparator with malfunction reduced and phase-locked state detecting circuit using the same
03/11/2004WO2004021573A1 Synchronous mirror delay (smd) circuit and method including a ring oscillator for timing coarse and fine delay intervals
03/11/2004WO2004021539A2 Transition detection at input of integrated circuit device
03/11/2004WO2004021270A1 Method for regulating the input signal of a non-contact transponder
03/11/2004US20040048574 Method and apparatus for adapting multi-band ultra-wideband signaling to interference sources
03/11/2004US20040047412 Pulse width control system for transmitting serial data
03/11/2004US20040047410 Method and apparatus for compensating for phase error of digital signal
03/11/2004US20040046596 Clock recovery circuit and electronic device using a clock recovery circuit
03/11/2004US20040046594 Programmable frequency multiplier
03/11/2004US20040046592 Comparator circuit
03/11/2004US20040046589 Source synchronous interface using variable digital data delay lines
03/11/2004US20040046209 When n-channel thin film transistors(TFTs) and p-channel TFTs are formed on a polycrystalline silicon film formed on a glass substrate, a process is included in which P-dopant or N-dopant is introduced at the same time to the channel region
03/11/2004DE10240134A1 Interpolating input values to produce output signal of different sampling rate but following same curve profile
03/10/2004CN1480814A Multiphace clock generating circuit
03/09/2004US6704372 Digital implementation of multi-channel demodulators
03/09/2004US6703957 Digital-to-analog converter
03/09/2004US6703888 Method of operating circuit with FET transistor pair
03/09/2004US6703883 Low current clock sensor
03/09/2004US6703879 Clock generation circuit, control method of clock generation circuit and semiconductor memory device
03/09/2004US6703872 High speed, high common mode range, low delay comparator input stage
03/04/2004WO2004019192A2 Clock generator for integrated circuit
03/04/2004US20040042573 Data detection circuit and method
03/04/2004US20040042257 Semiconductor memory device having partially controlled delay locked loop
03/04/2004US20040042255 Method and apparatus for latency specific duty cycle correction
03/04/2004US20040041947 Frequency controller
03/04/2004US20040041614 Amplitude converting circuit
03/04/2004US20040041612 Amplifiers with variable swing control
03/04/2004US20040041609 Methods and apparatus for duty cycle control
03/04/2004US20040041608 Pulse generating circuit and semiconductor device provided with same
03/04/2004US20040041607 Method and circuit for generating constant slew rate output signal
03/04/2004US20040041606 Synchronous mirror delay (smd) circuit and method including a ring oscillator for timing coarse and fine delay intervals
03/04/2004US20040041547 Device and method for inhibiting power fluctuation
03/03/2004CN1479186A Clock multiple circuit
03/03/2004CN1479144A Method for manufacturing liquid crystal display device
03/03/2004CN1140810C Full-wave level detector of integrated circuit
03/02/2004US6701506 Method for match delay buffer insertion
03/02/2004US6701444 Method and apparatus for process independent clock signal distribution
03/02/2004US6701340 Double differential comparator and programmable analog block architecture using same
03/02/2004US6700817 Semiconductor integrated circuit device with operation/function setting information memory
03/02/2004US6700722 High-speed zero phase restart of a multiphase clock
03/02/2004US6700532 Magnetron drive circuit
03/02/2004US6700438 Data comparator using non-inverting and inverting strobe signals as a dynamic reference voltage and input buffer using the same
03/02/2004US6700429 Semiconductor device
03/02/2004US6700427 Wideband DC-accurate series resistance compensator
03/02/2004US6700425 Multi-phase clock generators that utilize differential signals to achieve reduced setup and hold times
03/02/2004US6700423 Pulse width control circuit controlling pulse width of output light
03/02/2004US6700422 Apparatus for increasing slew rate
03/02/2004US6700420 Differential output structure with reduced skew for a single input
03/02/2004US6700416 Input buffer and method for voltage level detection
02/2004
02/26/2004WO2004017520A1 Digital circuit having a delay circuit for clock signal timing adjustment
02/26/2004WO2004017519A1 Method for the filtering of noise from measured signals
02/26/2004WO2003069358A3 Method and apparatus for providing information from a speed and direction sensor
02/26/2004WO2003021778A3 Monocycle generator
02/26/2004US20040037383 Data resynchronization circuit
02/26/2004US20040036643 Digital pixel sensor with a dynamic comparator having reduced threshold voltage sensitivity
02/26/2004US20040036510 Clock signal propagation gate and semiconductor integrated circuit including same
02/26/2004DE10309405A1 Wafer-Schaltung mit der Fähigkeit einer genauen Umwandlung eines analogen Signals zu einem digitalen Signal Wafer circuit with the ability of a precise conversion of an analog signal to a digital signal
02/25/2004EP1391038A2 Digital frequency multiplier
02/25/2004CN1477772A Inrush current limiting circuit for pulse frequency modwlation to control charge pump
02/25/2004CN1139988C Semiconductor integrated circuit
02/25/2004CN1139816C Peak detector using automatic threshold control and method thereof
02/24/2004US6696897 System and method for voltage controlled oscillator phase interpolation
02/24/2004US6696886 Automatically adjusting gain/bandwidth loop filter
02/24/2004US6696877 Level shift circuit
02/24/2004US6696876 Clock interpolation through capacitive weighting
02/24/2004US6696875 Pulse clock/signal delay apparatus and method
02/24/2004US6696868 Frequency to frequency de-randomizer circuit
02/24/2004US6696860 Variable voltage data buffers
02/19/2004WO2004015857A1 Sensor signal output circuit
02/19/2004WO2004015743A2 Clock distributor circuit for maintaining a phase relationship between remote operating nodes and a reference clock on a chip
02/19/2004WO2002097987A3 Method and system for managing a pulse width of a signal pulse
02/19/2004US20040032704 Delay circuit
02/19/2004US20040032301 Microwave pulse generator
02/19/2004DE10233218A1 Circuit for logic devices comprises part circuits having capacitors, resistances and clock signal inputs with individual delay adjustment
02/19/2004CA2494967A1 Clock distributor circuit for maintaining a phase relationship between remote operating nodes and a reference clock on a chip
02/18/2004CN1476194A Clock restoring circuit
02/18/2004CN1475808A Power position detecting circuit
02/18/2004CN1139186C Delayed high-voltage ns pulse driver
02/17/2004US6693466 Comparator circuit and infrared signal receiving apparatus
02/17/2004US6693465 Open input sense for differential receiver
02/17/2004US6693458 Apparatus for an optimized high speed comparator
02/12/2004WO2004014066A2 Method and devic the for setting the slice level in a binary signal
02/12/2004US20040030946 Clock distributor circuit for maintaining a phase relationship between remote operating nodes and a reference clock on a chip
02/12/2004US20040029313 Self-determining electronic control circuit
02/12/2004US20040028149 Programmable integrated DiSEqC transceiver
02/12/2004US20040028084 Signal delay structure in high speed bit stream demultiplexer
02/12/2004US20040028012 Flexible method and apparatus for encoding and decoding signals using a time division multiple frequency scheme
02/12/2004US20040027189 Circuit configuration for level boosting, in particular for driving a programmable link
02/12/2004US20040027183 Amplitude and rise-time sensitive timing-shaping filters with built-in pulse-tail cancellation for high count-rate operation
02/12/2004US20040027182 Duty-cycle correction circuit
02/12/2004US20040027178 Signal buffer for high-speed signal transmission and signal line driving circuit including the same