Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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11/10/1994 | WO1994026031A1 Dc-coupled active pull-down ecl circuit with self-adjusting drive capability |
11/10/1994 | WO1994026030A1 Noise isolated i/o buffer |
11/09/1994 | EP0623999A2 Field programmable gate array |
11/09/1994 | CN1026543C 信号延迟电路 Signal delay circuit |
11/08/1994 | US5363332 Current-driven signal interface implemented in semiconductor integrated circuit device |
11/08/1994 | US5362999 EPLD chip with hybrid architecture optimized for both speed and flexibility |
11/08/1994 | US5362998 Composite circuit of bipolar transistors and MOS transistors and semiconductor integrated circuit device using the same |
11/08/1994 | US5362997 BiCMOS output driver |
11/08/1994 | US5362996 Staggered output circuit for noise reduction |
11/08/1994 | US5362995 Voltage comparing circuit |
11/03/1994 | DE2858738C2 Method for producing an integrated circuit for inverting a binary logic signal |
11/02/1994 | EP0622903A2 Input buffer circuit having sleep mode and bus hold function |
11/02/1994 | EP0225924B1 Electronic memory element with a lambda transistor |
11/01/1994 | US5361042 Compensated offset voltage, low gain, high bandwidth, full swing, wide common mode range, CMOS differential voltage amplifier |
11/01/1994 | US5361006 Electrical circuitry with threshold control |
11/01/1994 | US5361005 Configurable driver circuit and termination for a computer input/output bus |
11/01/1994 | US5361004 TTL-CMOS output stage for an integrated circuit |
11/01/1994 | US5361003 Adjustable buffer driver |
11/01/1994 | US5361002 Voltage compensating CMOS input buffer |
10/27/1994 | WO1994024797A1 High-speed, differential line driver |
10/27/1994 | WO1994024765A1 Sequentially clocked domino-logic cells |
10/27/1994 | WO1994024764A1 Ecl and ttl to cmos logic converter |
10/27/1994 | WO1994024763A1 Power management for programmable logic devices |
10/27/1994 | DE4337888A1 High frequency circuit with output driver |
10/26/1994 | EP0621695A2 Integrated circuit with an active-level configurable pin and method therefor |
10/26/1994 | EP0621694A2 Low power interface circuit |
10/26/1994 | EP0621693A2 BiCMOS output driver circuit |
10/26/1994 | EP0621692A2 Overvoltage protection circuitry |
10/26/1994 | EP0621691A2 Complementary-signal BiCMOS line driver with low skew |
10/26/1994 | EP0621690A2 Reset logic circuit and method |
10/25/1994 | US5359562 Semiconductor memory having polycrystalline silicon load resistors and CMOS peripheral circuitry |
10/25/1994 | US5359553 Low power ECL/MOS level converting circuit and memory device and method of converting a signal level |
10/25/1994 | US5359536 Programmable gate array with improved interconnect structure, input/output structure and configurable logic block |
10/25/1994 | US5359243 Fast TTL to CMOS level converting buffer with low standby power |
10/25/1994 | US5359242 Programmable logic with carry-in/carry-out between logic blocks |
10/25/1994 | US5359241 ECL circuit |
10/25/1994 | US5359240 Low power digital signal buffer circuit |
10/25/1994 | US5359239 Output circuit with reduced switching noise |
10/25/1994 | US5359234 Circuit and method of sensing process and temperature variation in an integrated circuit |
10/25/1994 | US5359210 Integrated circuit |
10/19/1994 | EP0620650A2 Interface circuit |
10/19/1994 | EP0620649A2 Transceiver circuit for an integrated circuit |
10/19/1994 | EP0620648A2 Circuit |
10/19/1994 | EP0619926A1 Complementary logic with n-channel output transistors |
10/19/1994 | EP0467971B1 High speed complementary field effect transistor logic circuits |
10/18/1994 | US5357548 Reversible charge transfer and logic utilizing them |
10/18/1994 | US5357522 Test circuit of input/output macrocell of erasable and programmable logic device |
10/18/1994 | US5357461 Output unit incorporated in semiconductor integrated circuit for preventing semiconductor substrate from fluctuating in voltage level |
10/18/1994 | US5357416 Voltage generating circuit causing no threshold voltage loss by FET in output voltage |
10/18/1994 | US5357154 Level converter circuit for converting ECL-level input signals |
10/18/1994 | US5357153 Macrocell with product-term cascade and improved flip flop utilization |
10/18/1994 | US5357152 Logic system of logic networks with programmable selected functions and programmable operational controls |
10/18/1994 | US5357151 Intrinsically safe logic and-circuit having two inputs |
10/13/1994 | WO1994023500A1 Programmable logic device having security elements located amongst configuration bit locations to prevent unauthorized reading |
10/13/1994 | WO1994022664A1 Photohardening molding apparatus with recoater travelling stroke regulating mechanism |
10/12/1994 | EP0619652A2 Data output circuit |
10/11/1994 | US5355127 Method and apparatus for transferring information by utilizing electron beam |
10/11/1994 | US5355035 High speed BICMOS switches and multiplexers |
10/11/1994 | US5355033 Data input buffer circuit for use in a semiconductor memory device |
10/11/1994 | US5355032 TTL to CMOS translator circuit and method |
10/11/1994 | US5355031 Complementary logic with n-channel output transistors |
10/11/1994 | US5355030 Low voltage BICMOS logic switching circuit |
10/11/1994 | US5355029 Staged CMOS output buffer |
10/11/1994 | US5355028 Lower power CMOS buffer amplifier for use in integrated circuit substrate bias generators |
10/05/1994 | EP0618584A1 Method and circuit for configuring I/O devices |
10/04/1994 | US5353114 Opto-electronic interferometic logic |
10/04/1994 | US5353028 Differential fuse circuit and method utilized in an analog to digital converter |
10/04/1994 | US5352943 ECL to GaAs logic level shift interface circuit |
10/04/1994 | US5352942 Gate array semiconductor circuit device, input circuit, output circuit and voltage lowering circuit |
10/04/1994 | US5352941 CMOS/ECL level converting circuit |
10/04/1994 | US5352940 Ram convertible look-up table based macrocell for PLDs |
10/04/1994 | US5352939 Master slice semiconductor integrated circuit with output drive current control |
09/29/1994 | WO1994022223A1 Epld chip with hybrid architecture optimized for both speed and flexibility |
09/29/1994 | WO1994022222A1 Dynamic control of configurable logic |
09/29/1994 | WO1994022221A1 Noninverting bi-cmos gates with propagation delays of a single bi-cmos inverter |
09/29/1994 | WO1994022220A1 Differential- to single-ended cmos converter |
09/29/1994 | WO1994022142A1 Random access memory (ram) based configurable arrays |
09/29/1994 | DE4406489A1 Device for forwarding a transmission signal |
09/29/1994 | CA2158467A1 Random access memory (ram) based configurable arrays |
09/28/1994 | EP0617513A2 Field programmable gate array with direct input/output connection |
09/28/1994 | EP0617295A2 Superconducting magnetometer with digital output |
09/28/1994 | EP0616725A1 Electrical isolation in integrated circuits |
09/27/1994 | US5350954 Programmable logic array apparatus |
09/21/1994 | EP0616432A2 Sense amplifier |
09/21/1994 | EP0616431A1 Input buffer utilizing a cascode |
09/21/1994 | EP0616430A2 Buffer circuit |
09/21/1994 | EP0615639A1 Digital circuits |
09/20/1994 | US5349691 Programming process for 3-level programming logic devices |
09/20/1994 | US5349544 Programmable system synchronizer |
09/20/1994 | US5349255 Programmable tco circuit |
09/20/1994 | US5349253 Logic translator interfacing between five-volt TTL/CMOS and three-volt CML |
09/20/1994 | US5349250 Logic structure and circuit for fast carry |
09/20/1994 | US5349249 Programmable logic device having security elements located amongst configuration bit location to prevent unauthorized reading |
09/20/1994 | US5349248 Adaptive programming method for antifuse technology |
09/20/1994 | US5349247 Enhancement circuit and method for ensuring diactuation of a switching device |
09/20/1994 | US5349243 Latch controlled output driver |
09/15/1994 | WO1994021046A1 Complementary macrocell feedback circuit |
09/15/1994 | WO1994021045A1 Charge recovery logic including split level logic |
09/13/1994 | US5347519 Preprogramming testing in a field programmable gate array |
09/13/1994 | US5347184 Dual receiver edge-triggered digital signal level detection system |