Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
12/1996
12/31/1996US5589783 Variable input threshold adjustment
12/31/1996US5589782 Macrocell and clock signal allocation circuit for a programmable logic device (PLD) enabling PLD resources to provide multiple functions
12/31/1996US5589761 Dual polarity voltage regulator circuits and methods for providing voltage regulation
12/31/1996US5589404 Monolithically integrated VLSI optoelectronic circuits and a method of fabricating the same
12/27/1996WO1996042141A1 Field programmable gate array (fpga) having an improved configuration memory and look up table
12/27/1996WO1996042140A1 Field programmable gate array (fpga) with interconnect encoding
12/27/1996WO1996042139A1 Input receiver, output driver, and input/output driver circuits capable of high voltage operation for an integrated circuit
12/27/1996WO1996042050A1 Circuit for comparing two electrical quantities provided by a first neuron mos field effect transistor and a reference source
12/27/1996WO1996042048A1 Circuit for producing logic elements representable by threshold equations
12/27/1996EP0750397A1 Switching circuit for selectively providing voltages of opposed signs
12/27/1996EP0750391A2 Wide-band amplifier
12/27/1996EP0750242A2 Semiconductor device having an output circuit for transmitting low-voltage differential signals
12/27/1996EP0639309B1 Asynchronous logic circuit for 2-phase operation
12/27/1996EP0583298B1 LOGIC CIRCUIT FOR ASYNCHRONOUS CIRCUITS WITH n-CHANNEL LOGIC BLOCK AND p-CHANNEL LOGIC BLOCK INVERSE THERETO
12/24/1996US5588006 Logic circuit having a control signal switching logic function and having a testing arrangement
12/24/1996US5587921 Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer
12/24/1996US5587709 High speed serial link for fully duplexed data communication
12/24/1996US5587678 Integrated circuit having an output stage with a Miller capacitor
12/24/1996US5587677 Combined CMOS and NPN output pull-up circuit
12/24/1996US5587672 Dynamic logic having power-down mode with periodic clock refresh for a low-power graphics controller
12/24/1996US5587671 Semiconductor device having an output buffer which reduces signal degradation due to leakage of current
12/24/1996US5587669 Programmable application specific integrated circuit and logic cell therefor
12/24/1996US5587668 Semiconductor devices utilizing neuron MOS transistors
12/24/1996US5587667 Output buffer circuit for high-speed logic operation
12/24/1996US5587666 Sense amplifier slew circuitry
12/24/1996US5587603 Two-transistor zero-power electrically-alterable non-volatile latch
12/19/1996WO1996041417A1 Glitch-free clock enable circuit
12/19/1996WO1996041416A1 Glitch-free clock enable circuit
12/19/1996DE19622646A1 CMOS logic gate integrated semiconductor device
12/19/1996DE19603447A1 Integrated semiconductor device with multiple integrated circuits for e.g. logic circuit
12/18/1996EP0749126A1 Tri-state programmable output interface device for CMOS memory
12/18/1996EP0749059A2 Telecommunication terminal with voltage regulator
12/18/1996EP0605707B1 Logic cell which can be configured as a transparent latch
12/17/1996US5586124 Strongly fail-safe interface based on concurrent checking
12/17/1996US5586044 Array of configurable logic blocks including cascadable lookup tables
12/17/1996US5585759 Input buffer of semiconductor integrated circuit
12/17/1996US5585744 Circuits systems and methods for reducing power loss during transfer of data across a conductive line
12/17/1996US5585743 ECL-CMOS level conversion circuit
12/17/1996US5585742 Bus drivers using skew compensation delay circuits for enabling tristate output buffers
12/17/1996US5585741 Impedance emulator
12/17/1996US5585740 CMOS low output voltage bus driver with controlled clamps
12/17/1996US5585288 Digital MMIC/analog MMIC structures and process
12/11/1996EP0748053A2 Programmable array interconnect latch
12/11/1996EP0748052A1 Continuous address structure with folding
12/11/1996EP0748051A2 System and method for dynamically reconfiguring a programmable gate array
12/11/1996EP0748050A1 Method and system for enhanced drive in programmable gate arrays
12/11/1996EP0748049A2 Interconnection architecture for coarse-grained programmable logic device
12/11/1996EP0748048A1 Low power, low voltage level shifter
12/11/1996EP0748047A1 Integrated buffer circuit
12/11/1996EP0748046A2 Connection of high going and low going transitions
12/11/1996EP0746934A1 A termination network and a control circuit
12/11/1996EP0746929A1 High speed differential receiver for data communications
12/10/1996US5583460 Output driver circuit for restraining generation of noise and semiconductor memory device utilizing such circuit
12/10/1996US5583457 Semiconductor integrated circuit device having power reduction mechanism
12/10/1996US5583456 Differentially coupled AND/NAND and XOR/XNOR circuitry
12/10/1996US5583455 Semiconductor logic circuit using a first power source and a second power source
12/10/1996US5583454 Programmable input/output driver circuit capable of operating at a variety of voltage levels and having a programmable pullup/pulldown function
12/10/1996US5583452 Tri-directional buffer
12/10/1996US5583451 Polarity control circuit which may be used with a ground bounce limiting buffer
12/10/1996US5583450 Sequencer for a time multiplexed programmable logic device
12/10/1996CA2110570C High-speed level shifter with simple circuit arrangement
12/05/1996WO1996038919A1 A programmable optimized-distribution logic allocator for a high-density complex pld
12/05/1996WO1996038918A1 A multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices
12/05/1996WO1996038917A1 Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation
12/05/1996WO1996038916A1 A programmable uniform symmetrical distribution logic allocator for a high-density complex pld
12/05/1996WO1996038915A1 Macrocell and clock signal allocation circuit for a programmable logic device (pld) enabling pld resources to provide multiple functions
12/05/1996WO1996038914A1 Semiconductor integrated circuit device and signal processor
12/05/1996WO1996038912A1 Variable delay circuit
12/04/1996EP0746107A2 Programmable logic cell
12/04/1996EP0746106A2 Programmable array I/O - routing resource
12/04/1996EP0746105A2 Programmable array clock/reset resource
12/04/1996EP0746104A1 Programmable array interconnect network
12/04/1996EP0746103A2 Programmable logic array integrated circuits
12/04/1996EP0746102A2 Programmable logic array integrated circuits
12/04/1996EP0746101A1 Circuit for detection and protection against short circuits for digital outputs
12/04/1996EP0746093A1 Operational amplifier
12/04/1996CN1137199A Flip-flop controller
12/03/1996US5581506 Level-shifter, semiconductor integrated circuit, and control methods thereof
12/03/1996US5581202 Semiconductor integrated circuit device and production method thereof
12/03/1996US5581201 Apparatus for unit control and presence detection
12/03/1996US5581200 Stored and combinational logic function generator without dedicated storage elements
12/03/1996US5581199 Interconnect architecture for field programmable gate array using variable length conductors
12/03/1996US5581198 Shadow DRAM for programmable logic devices
12/03/1996US5581197 Method of programming a desired source resistance for a driver stage
11/1996
11/28/1996WO1996037958A1 Supply and interface configurable input/output buffer
11/28/1996WO1996037957A1 Circuit arrangement of a clocked semiconductor final stage
11/28/1996DE19538463A1 Ausgangs-Pufferspeicher mit niedrigem Rauschen und hohem Ansteuerungsvermögen Output buffer with low noise and high driving capability
11/28/1996DE19518860A1 Schaltungsanordnung einer getakteten Halbleiterendstufe Circuitry of a clocked semiconductor amplifier
11/27/1996EP0744835A2 Improved programmable gate array
11/27/1996EP0744704A2 Logic synthesis method, semiconductor integrated circuit and arithmetic circuit
11/27/1996EP0744687A1 Combinational logic circuit
11/27/1996EP0744097A1 Terminating transmission line impedance-matching circuit
11/27/1996CN1136867A Singalling system
11/27/1996CN1136730A Reference voltage semiconductor device
11/27/1996CN1136727A Temperature compensation piezoelectric oscillator
11/26/1996US5579276 Internal voltage boosting circuit in a semiconductor memory device
11/26/1996US5578955 Signal supply circuit
11/26/1996US5578944 Signal receiver and apparatus incorporating same
11/26/1996US5578943 Signal transmitter and apparatus incorporating same
11/26/1996US5578941 Voltage compensating CMOS input buffer circuit
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