| Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996) |
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| 07/01/1997 | US5644217 Emitter coupled logic output circuit |
| 06/26/1997 | WO1997023046A1 Precharged adiabatic pipelined logic |
| 06/26/1997 | WO1997023045A1 Asynchronous self-adjusting input circuit |
| 06/26/1997 | WO1997023044A1 Deconvolution input buffer compensating for capacitance of a switch matrix of a high density programmable logic device |
| 06/26/1997 | WO1997017763A3 Universal receiver device |
| 06/26/1997 | DE19651548A1 CMOS output circuit with precharging circuit |
| 06/26/1997 | DE19601630C1 Signal level converter circuit with two CMOS inverting stages |
| 06/25/1997 | EP0780984A1 Output circuit and electronic device using the circuit |
| 06/25/1997 | EP0780983A2 Voltage level shifter |
| 06/25/1997 | EP0780846A2 Field programmable memory array |
| 06/25/1997 | EP0780752A1 Improvements in or relating to control circuits |
| 06/25/1997 | EP0780037A2 A method for testing an electronic circuit by logically combining clock signals, and an electronic circuit provided with facilities for such testing |
| 06/25/1997 | EP0780017A1 System comprising field programmable gate array and intelligent memory |
| 06/24/1997 | US5642272 Apparatus and method for device power-up using counter-enabled drivers |
| 06/24/1997 | US5642061 Short circuit current free dynamic logic clock timing |
| 06/24/1997 | US5642059 Bus driver circuit with overvoltage protection |
| 06/24/1997 | US5642058 Periphery input/output interconnect structure |
| 06/19/1997 | DE19651465A1 Digital data level control circuit for audio volume, balance, or tone controls |
| 06/18/1997 | EP0779705A2 Inverted amplifying circuit |
| 06/18/1997 | EP0779664A2 Apparatus comprising a heterojunction bipolar transistor |
| 06/18/1997 | EP0779568A2 Programmable bandwidth voltage regulator |
| 06/18/1997 | EP0778999A1 High speed digital buffer, driver or level shifter circuit |
| 06/18/1997 | CN1152375A Architecture and interconnect scheme for programmable logic circuits |
| 06/18/1997 | CN1152215A Setter of system resetting state |
| 06/18/1997 | CN1152175A Output buffer with antistatic capacity |
| 06/17/1997 | US5640348 Non-volatile semiconductor memory |
| 06/17/1997 | US5640123 Substrate voltage control circuit for a flash memory |
| 06/17/1997 | US5640108 Single stage dynamic receiver/decoder |
| 06/17/1997 | US5640106 Method and structure for loading data into several IC devices |
| 06/17/1997 | US5640105 Current mode null convention threshold gate |
| 06/17/1997 | US5640104 Signal receiver in an interface |
| 06/12/1997 | WO1997021273A1 A programmable input/output driver circuit capable of operating at a variety of voltage levels and having a programmable pull up/pull down function |
| 06/12/1997 | WO1997021272A1 Circuit comprising a bus conductor and a bus interface circuit |
| 06/12/1997 | WO1997021271A1 Fail-safe timer circuit and on-delay circuit using the same |
| 06/12/1997 | DE19622972A1 Negative voltage generator e.g. for GaAs-FET amplifier |
| 06/11/1997 | EP0778673A1 Integrated circuit with programmable pad-driver |
| 06/11/1997 | EP0778672A2 Integrated circuit output buffer |
| 06/11/1997 | EP0777935A1 Signalling system |
| 06/11/1997 | EP0777874A2 Pipelined data processing circuit |
| 06/11/1997 | EP0696393A4 Dc-coupled active pull-down ecl circuit with self-adjusting drive capability |
| 06/11/1997 | CN2256195Y Human body inducting electronic ignition controller |
| 06/11/1997 | CN1151636A Flip-flop circuit operating on low voltage |
| 06/10/1997 | US5638328 Data output buffers and methods having a clamp function |
| 06/10/1997 | US5638008 Method and apparatus for generating an asynchronously clocked signal in a synchronously clocked programmable device |
| 06/10/1997 | US5638007 In an output driver |
| 06/10/1997 | US5637900 Latchup-free fully-protected CMOS on-chip ESD protection circuit |
| 06/05/1997 | WO1997020391A1 Integrated drivers for flat panel displays employing chalcogenide logic elements |
| 06/05/1997 | WO1997020390A1 A bus driver circuit configured to partially discharge a bus conductor to decrease line to line coupling capacitance |
| 06/05/1997 | WO1997020389A1 Low voltage logic circuit |
| 06/05/1997 | DE19609078C1 Threshold logic circuit using neuron transistors |
| 06/04/1997 | EP0777331A2 Programmable driver circuit for multi-source buses |
| 06/04/1997 | EP0777330A2 PECL buffer |
| 06/04/1997 | EP0777329A2 A BiMOS logic circuit directly controllable by a CMOS block formed on same IC chip |
| 06/04/1997 | EP0708939B1 Optimization circuit |
| 06/03/1997 | US5636169 Precharge voltage generator |
| 06/03/1997 | US5635867 High performance drive structure for MOSFET power switches |
| 06/03/1997 | US5635861 Off chip driver circuit |
| 06/03/1997 | US5635860 Overvoltage-tolerant self-biasing CMOS output buffer |
| 06/03/1997 | US5635859 Level converting circuit |
| 06/03/1997 | US5635857 IC chip using a common multiplexor logic element for performing logic operations |
| 06/03/1997 | US5635856 High speed programmable macrocell with combined path for storage and combinatorial modes |
| 06/03/1997 | US5635855 Method for simultaneous programming of in-system programmable integrated circuits |
| 06/03/1997 | US5635854 Programmable logic integrated circuit including verify circuitry for classifying fuse link states as validly closed, validly open or invalid |
| 06/03/1997 | US5635851 Read and writable data bus particularly for programmable logic devices |
| 05/29/1997 | WO1997019516A1 A clocked high voltage switch |
| 05/29/1997 | CA2209295A1 A clocked high voltage switch |
| 05/28/1997 | EP0776093A2 Configurable logic array |
| 05/28/1997 | EP0776046A1 SOI CMOS logic circuit with transfer gates |
| 05/28/1997 | EP0775404A1 High-speed, differential line driver |
| 05/28/1997 | EP0689712A4 Random access memory (ram) based configurable arrays |
| 05/28/1997 | DE19605628C1 Circuit for avoiding electrostatic discharge and latch-up |
| 05/27/1997 | US5634061 Instruction decoder utilizing a low power PLA that powers up both AND and OR planes only when successful instruction fetch signal is provided |
| 05/27/1997 | US5633830 Random access memory block circuitry for programmable logic array integrated circuit devices |
| 05/27/1997 | US5633820 Self-resetting CMOS parallel adder with a bubble pipelined architecture, tri-rail merging logic, and enhanced testability |
| 05/27/1997 | US5633806 Semiconductor integrated circuit and method of designing same |
| 05/27/1997 | US5633611 Complementary current source circuit |
| 05/27/1997 | US5633604 Mixed mode output buffer circuit for CMOSIC |
| 05/27/1997 | US5633603 Data output buffer using pass transistors biased with a reference voltage and a precharged data input |
| 05/27/1997 | US5633602 Low voltage CMOS to low voltage PECL converter |
| 05/27/1997 | US5633601 Field programmable gate array logic module configurable as combinational or sequential circuits |
| 05/27/1997 | US5633600 Output buffer circuit having a minimized output voltage propagation |
| 05/22/1997 | WO1997018632A1 An active pull-down circuit for ecl using a capacitive-discharge coupled charge pump |
| 05/21/1997 | EP0774839A2 Negative resistance element for multivalue to binary conversion |
| 05/21/1997 | EP0774838A1 CMOS interface for coupling a low voltage integrated circuit with devices powered at a higher supply voltage |
| 05/21/1997 | EP0774836A2 Latch circuit for receiving small amplitude signals |
| 05/20/1997 | US5631854 Data link module for time division multiplexing control systems |
| 05/20/1997 | US5631597 Negative voltage circuit for a flash memory |
| 05/20/1997 | US5631589 Transition control circuit for driver circuits |
| 05/20/1997 | US5631581 Microelectronic integrated circuit including triangular semiconductor "and" gate device |
| 05/20/1997 | US5631580 BICMOS ECL-CMOS level converter |
| 05/20/1997 | US5631579 Output buffer circuit for interfacing semiconductor integrated circuits operating on different supply voltages |
| 05/20/1997 | US5631578 Programmable array interconnect network |
| 05/20/1997 | US5631577 Synchronous dual port RAM |
| 05/20/1997 | US5631576 Programmable logic array integrated circuit devices with flexible carry chains |
| 05/15/1997 | WO1997017763A2 Universal receiver device |
| 05/15/1997 | WO1997017762A1 An input/output driver circuit for isolating with minimal power consumption a peripheral component from a core section |
| 05/15/1997 | WO1997015116A3 Tspc latches and flipflops |
| 05/15/1997 | DE19541734A1 Schaltungsanordnung zur Durchführung eines Reset Circuit arrangement for carrying out a reset |
| 05/15/1997 | CA2236785A1 Universal receiver device |
| 05/14/1997 | EP0773448A1 Leakage current control system for low voltage CMOS circuits |