Patents
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
04/2006
04/26/2006CN1765054A Reconfigurable logical circuit using transistor having spin-dependent transmission characteristics
04/26/2006CN1764071A Circuit device of OR gate circuit for providing dual monitoring signal
04/26/2006CN1764070A Circuit device of AND gate circuit for providing dual monitoring signal
04/26/2006CN1764069A Voltage level converter
04/26/2006CN1254017C Automatic switching circuit of pulse signal
04/26/2006CN1254016C Electric circuits without burst waves and for reducing electromagnetic interference
04/26/2006CN1254013C Correction circuit, delay circuit and annular oscillator circuit
04/26/2006CN1254012C Method for controlling comparator with fine controllable hysteresis region
04/25/2006US7036105 Integrated circuits with at least one layer that has more than one preferred interconnect direction, and method for manufacturing such IC's
04/25/2006US7035945 Method and apparatus for identifying computer expansion cards
04/25/2006US7035893 4-2 Compressor
04/25/2006US7035833 System which extracts feature from fuzzy information and semiconductor integrated circuit device having the system
04/25/2006US7035148 Output driver capable of controlling slew rate of output signal according to operating frequency information or CAS latency information
04/25/2006US7035128 Semiconductor memory device and semiconductor integrated circuit device
04/25/2006US7034616 Operational amplification circuit, overheat detecting circuit and comparison circuit
04/25/2006US7034598 Switching point detection circuit and semiconductor device using the same
04/25/2006US7034594 Differential master/slave CML latch
04/25/2006US7034578 N-domino output latch with accelerated evaluate path
04/25/2006US7034577 Variable timing circuit
04/25/2006US7034576 Pulsed dynamic keeper gating
04/25/2006US7034575 Variable impedence output buffer
04/25/2006US7034574 Low-voltage differential signal (LVDS) transmitter with high signal integrity
04/25/2006US7034573 Level shifter without DC current flow
04/25/2006US7034572 Voltage level shifting circuit and method
04/25/2006US7034571 Level converting circuit efficiently increasing an amplitude of a small-amplitude signal
04/25/2006US7034570 I/O cell configuration for multiple I/O standards
04/25/2006US7034569 Programmable system on a chip for power-supply voltage and current monitoring and control
04/25/2006US7034568 Logic circuit
04/25/2006US7034567 Semiconductor devices with reference voltage generators and termination circuits configured to reduce termination mismatch
04/25/2006US7034566 Method and circuit for increased noise immunity for clocking signals in high speed digital systems
04/25/2006US7034565 On-die termination circuit and method for reducing on-chip DC current, and memory system including memory device having the same
04/20/2006WO2006042315A2 Asics having more features than generally usable at one time and methods of use
04/20/2006WO2006040904A1 Level shifter circuit, drive circuit, and display
04/20/2006WO2006040706A2 Low voltage, high-speed output-stage for laser or modulator driving
04/20/2006WO2006004913A3 Single event upset immune keeper circuit and method for dual redundant dynamic logic
04/20/2006WO2005119915A3 Current mode logic buffer
04/20/2006WO2005119471A3 Bus controller
04/20/2006WO2005117263A3 High speed clock distribution transmission line network
04/20/2006US20060085781 Library for computer-based tool and related system and method
04/20/2006US20060085779 Representing device layout using tree structure
04/20/2006US20060083052 Self reverse bias low-power high-performance storage circuitry and related methods
04/20/2006US20060082482 Reference buffer with dynamic current control
04/20/2006US20060082389 Dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control
04/20/2006US20060082388 Logic circuitry
04/20/2006US20060082387 Energy recovery boost logic
04/20/2006US20060082386 Methods and systems for multi-state switching using multiple ternary switching inputs
04/20/2006US20060082385 Synchronous first-in/first-out block memory for a field programmable gate array
04/20/2006US20060082384 Multi-threshold complementary metal-oxide semiconductor (MTCMOS) bus circuit and method for reducing bus power consumption via pulsed standby switching
04/20/2006US20060082383 Pseudo differential output buffer, memory chip and memory system
04/20/2006US20060082382 Input circuit and an electronic control unit provided with such an input circuit
04/20/2006US20060082381 Output circuit
04/20/2006DE102005046678A1 Fahrzeugkommunikationssystem Vehicle communication system
04/19/2006CN1252931C Input/output buffer
04/19/2006CN1252930C Complementary input dynamic logic circuit and method of evaluating complex dynamic logic function
04/19/2006CN1252929C Complementary input dynamic multiplex decoding device and method
04/19/2006CN1252928C Complementary type input dynamic logic circuit and method of evaluating complex dynamic logic function
04/19/2006CN1252927C Semiconductor integrated circuit
04/19/2006CN1252820C Semiconductor integrated circuit device with body bias circuit
04/19/2006CN1252658C Control and monitoring signal transmission system
04/18/2006US7032058 Apparatus and method for topography dependent signaling
04/18/2006US7032057 Integrated circuit with transmit phase adjustment
04/18/2006US7032037 Server blade for performing load balancing functions
04/18/2006US7030666 Organic semiconductor inverting circuit
04/18/2006US7030665 Variable drive current driver circuit
04/18/2006US7030664 Half-rail differential driver circuit
04/18/2006US7030660 Line driver
04/18/2006US7030659 Signal switch with reduced on resistance and undershoot protection
04/18/2006US7030658 Systems and methods for operating logic circuits
04/18/2006US7030657 High speed signaling system with adaptive transmit pre-emphasis and reflection cancellation
04/18/2006US7030656 Low voltage differential signaling device with feedback compensation
04/18/2006US7030655 Memory interface system
04/18/2006US7030654 Low voltage to extra high voltage level shifter and related methods
04/18/2006US7030652 LUT-based logic element with support for Shannon decomposition and associated method
04/18/2006US7030651 Programmable structured arrays
04/18/2006US7030650 Fracturable incomplete look up table area efficient logic elements
04/18/2006US7030649 Integrated circuit including programmable logic and external-device chip-enable override control
04/18/2006US7030648 High performance interconnect architecture for field programmable gate arrays
04/18/2006US7030646 Functional pre-configuration of a programmable logic device
04/18/2006US7030644 Low reflection driver for a high speed simultaneous bidirectional data bus
04/18/2006US7030643 Output buffer circuits including logic gates having balanced output nodes
04/13/2006WO2006026019A3 Apparatus and method of interconnecting nanoscale programmable logic array clusters
04/13/2006US20060080631 ASICs having more features than generally usable at one time and methods of use
04/13/2006US20060080490 USB controller with intelligent transmission mode switching function and the operating method thereof
04/13/2006US20060077198 Level converter circuit and a liquid crystal display device employing the same
04/13/2006US20060077078 Command user interface with programmable decoder
04/13/2006US20060076980 Output driver and method thereof
04/13/2006US20060076979 Prestage for an off-chip driver (OCD)
04/13/2006US20060076978 Protection device for bus systems
04/13/2006US20060076977 USB 1.1 for USB OTG implementation
04/13/2006US20060076976 Data acceleration device and data transmission apparatus using the same
04/13/2006US20060076975 Reduced device count level shifter with power savings
04/13/2006US20060076974 Architecture and interconnect scheme for programmable logic circuits
04/13/2006US20060076610 Semiconductor integrated circuit device with reduced leakage current
04/13/2006DE60203032T2 Integrierte Halbleiterschaltung A semiconductor integrated circuit
04/13/2006DE19958144B4 Programmierbare Zwischenverbindungszelle zum wahlweisen Verbinden von Schaltkreisknoten in einem integrierten Schaltkreis und Anordnung programmierbarer Zwischenverbindungszellen Programmable interconnect cell for selectively connecting circuit nodes in an integrated circuit and array of programmable interconnect cells
04/13/2006DE19503964B4 Datenausgabepuffer einer Halbleitervorrichtung Data output buffer of a semiconductor device
04/13/2006DE102005001938B3 Stable reconfigurable digital logic system has several cells with magnetic layers, whose electrical resistance is altered by magnetic field pulses and has data cells in parallel with configuration cells
04/13/2006DE102004047664A1 Schaltung und Verfahren zum Erzeugen eines Ausgangssignals Circuit and method for generating an output signal
04/13/2006DE10146491B4 Elektronische Schaltung mit einer Treiberschaltung An electronic circuit comprising a driver circuit
04/12/2006EP1644979A2 Columnar architecture for pla or fpga