Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
08/2008
08/21/2008WO2008101036A1 Dynamic leakage control using selective back-biasing
08/21/2008WO2008100523A2 Low-power clock generation and distribution circuitry
08/21/2008WO2008042109A3 Structure cluster and method in programmable logic circuit
08/21/2008WO2008024274A3 Dual mode aes implementation to support single and multiple aes operations
08/21/2008US20080201682 Method of designing wiring structure of semiconductor device and wiring structure designed accordingly
08/21/2008US20080197905 Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers
08/21/2008US20080197884 Kick Gate
08/21/2008US20080197883 Integrated circuit device and electronic instrument
08/21/2008US20080197882 Logic circuits
08/21/2008US20080197881 Receiver circuit using nanotube-based switches and logic
08/21/2008US20080197880 Source driver and level shifting method thereof
08/21/2008US20080197879 Apparatus and method for a programmable logic device having improved look up tables
08/21/2008US20080197878 Enhanced field programmable gate array
08/21/2008US20080197877 Per byte lane dynamic on-die termination
08/21/2008US20080197876 Integrated circuit, system and method including a performance test mode
08/21/2008US20080197875 Integrated circuit
08/21/2008DE10212950B4 Pegelwandler, Signalwandlungsvorrichtung und Signalwandlungsverfahren Level converter, signal conversion apparatus and signal conversion method
08/20/2008EP1958332A2 Dynamic constant folding of a circuit
08/20/2008EP1618665B1 Flip-flop circuit assembly
08/20/2008EP1226502B1 Electronically moveable terminator and method for using same in a memory system
08/20/2008EP1142119B1 On-chip decoupling capacitor system with parallel fuse
08/20/2008EP1034479B1 TEST CIRCUITRY FOR ASICs
08/20/2008CN101248582A Voltage-level shifter
08/20/2008CN101247114A Oscillator
08/20/2008CN101246418A Heat insulation FIFO circuit based on CTGAL
08/20/2008CN100413072C Semiconductor integrated circuit device
08/20/2008CN100412942C Display device
08/20/2008CN100412801C Processor and integrated circuit comprising reconfigurable circuit
08/19/2008US7415683 Method and apparatus for a chaotic computing module
08/19/2008US7415681 Optimal mapping of LUT based FPGA
08/19/2008US7414454 Voltage switching circuit
08/19/2008US7414453 Level conversion circuit
08/19/2008US7414437 Nanomechanical computer
08/19/2008US7414436 Limited switch dynamic logic cell based register
08/19/2008US7414435 Circuit arrangement and method for converting logic signal levels and use of the circuit arrangement
08/19/2008US7414434 Input circuit
08/19/2008US7414433 Interconnect structure enabling indirect routing in programmable logic
08/19/2008US7414432 Dedicated logic cells employing sequential logic and control logic functions
08/19/2008US7414431 Dedicated logic cells employing configurable logic and dedicated logic functions
08/19/2008US7414430 Programmable logic device having an embedded differential clock tree
08/19/2008US7414429 Integration of high-speed serial interface circuitry into programmable logic device architectures
08/19/2008US7414428 Non-volatile memory configuration scheme for volatile-memory-based programmable circuits in an FPGA
08/19/2008US7414426 Time multiplexed dynamic on-die termination
08/14/2008WO2008097932A2 Die apparatus having configurable input/output and control method thereof
08/14/2008WO2008097339A2 Ballistic deflection transistor and logic circuits based on same
08/14/2008WO2008076546A3 Method and device for managing a power supply power-on sequence
08/14/2008US20080195878 Control Scheme for Binary Control of a Performance Parameter
08/14/2008US20080191988 Driving Method of an Electric Circuit
08/14/2008US20080191784 Ac Coupling And Gate Charge Pumping For Nmos And Pmos Device Control
08/14/2008US20080191745 High-speed differential receiver
08/14/2008US20080191744 Programmable current generator, current generation method and transmitter arrangement
08/14/2008US20080191743 Level shifter
08/14/2008US20080191742 Receiver circuit using nanotube-based switches and transistors
08/14/2008US20080191741 Integrated Circuit Having Configurable Cells and a Secured Test Mode
08/14/2008US20080191740 Clock tree network in a field programmable gate array
08/14/2008US20080191739 Method and apparatus for universal program controlled bus architecture
08/14/2008US20080191738 Three dimensional integrated circuits
08/14/2008US20080191737 Reconfigurable sequencer structure
08/14/2008US20080191736 Configurable ic with packet switch network
08/14/2008US20080191735 Accessing multiple user states concurrently in a configurable IC
08/14/2008US20080191733 Configurable ic with trace buffer and/or logic analyzer functionality
08/14/2008DE10352812B4 Verfahren und Schaltungsanordnung zur Erzeugung ternärer Signale Method and circuit for generating ternary signals
08/13/2008EP1956713A1 Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array
08/13/2008EP1956709A2 Switch driver circuit with a high side level shifter for transmitting an input signal and corresponding method
08/13/2008CN101242180A Voltage level conversion circuit and voltage level conversion method
08/13/2008CN101242179A Electronic system, semiconductor integrated circuit and terminal device
08/13/2008CN101242178A Semiconductor device and shift register circuit
08/13/2008CN101242177A Semiconductor device and display appliance using the semiconductor device
08/13/2008CN101242165A High pass filter circuit with low corner frequency
08/13/2008CN101242160A Two-stage operational amplifier with class ab output stage
08/13/2008CN101242137A Power-on-reset circuit and method for producing power-on-reset signal
08/13/2008CN101242133A Control circuit with TOP level regulator and corresponding method
08/13/2008CN100411139C Special semiconductor circuit and resource configuration method for semiconductor circuit driver
08/12/2008US7412679 Semiconductor integrated circuit and semiconductor integrated circuit manufacturing method
08/12/2008US7411585 Driving voltage generation device and method for controlling driving voltage generation device
08/12/2008US7411425 Method for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit
08/12/2008US7411424 Programmable logic function generator using non-volatile programmable memory switches
08/12/2008US7411423 Logic activation circuit
08/12/2008US7411422 Driver/equalizer with compensation for equalization non-idealities
08/12/2008US7411421 Apparatus and method for generating differential signal using single-ended drivers
08/12/2008US7411420 High-speed input signal receiver circuit
08/12/2008US7411419 Input/output systems and methods
08/12/2008US7411418 Efficient representation of state transition tables
08/12/2008US7411417 Selective loading of configuration data into configuration memory cells
08/12/2008US7411415 Bus termination scheme having concurrently powered-on transistors
08/12/2008US7411414 Single-ended output driver buffer
08/12/2008US7411413 Pulse latch circuit and semiconductor integrated circuit
08/12/2008US7411412 Semiconductor integrated circuit
08/12/2008US7411411 Methods and systems for hardening a clocked latch against single event effects
08/12/2008US7411318 Digital circuit having correcting circuit and electronic apparatus thereof
08/12/2008US7411267 Semiconductor integrated circuit device
08/07/2008WO2008093487A1 Inverter circuit
08/07/2008WO2008024704A3 Hysteresis comparator with programmable hysteresis width
08/07/2008US20080186059 Semiconductor integrated circuit
08/07/2008US20080186058 Level shifter for gate driver
08/07/2008US20080186057 Low frequency detector including common input voltage sensor
08/07/2008US20080186056 Programmable high-speed interface
08/07/2008US20080186054 Design structure for a flexible multimode logic element for use in a configurable mixed-logic signal distribution path
08/07/2008US20080186053 Die apparatus having configurable input/output and control method thereof
08/07/2008US20080186052 Methods, systems, and computer program products for using direct memory access to initialize a programmable logic device
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