Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
09/2014
09/18/2014US20140264639 Gate stack of boron semiconductor alloy, polysilicon and high-k gate dielectric for low voltage applications
09/18/2014US20140264638 Gate stack of boron semiconductor alloy, polysilicon and high-k gate dielectric for low voltage applications
09/18/2014US20140264637 Strip-ground field plate
09/18/2014US20140264636 Asymmetric cyclic depositon and etch process for epitaxial formation mechanisms of source and drain regions
09/18/2014US20140264635 RF Switch on High Resistive Substrate
09/18/2014US20140264634 Finfet for rf and analog integrated circuits
09/18/2014US20140264633 Finfet devices having a body contact and methods of forming the same
09/18/2014US20140264632 Semiconductor structure including a transistor having a layer of a stress-creating material and method for the formation thereof
09/18/2014US20140264627 Multi-gate transistor
09/18/2014US20140264626 Method for forming a gate electrode of a semiconductor device, gate electrode structure for a semiconductor device and according semiconductor device structure
09/18/2014US20140264624 Metal Gate Structure and Method
09/18/2014US20140264622 Semiconductor device
09/18/2014US20140264619 Gate pad and gate feed breakdown voltage enhancement
09/18/2014US20140264618 Isolation structure
09/18/2014US20140264613 Integrated circuits and methods for fabricating integrated circuits with active area protection
09/18/2014US20140264612 Growth of epitaxial semiconductor regions with curved top surfaces
09/18/2014US20140264610 Metal oxide semiconductor (mos) isolation schemes with continuous active areas separated by dummy gates and related methods
09/18/2014US20140264608 Ditches near semiconductor fins and methods for forming the same
09/18/2014US20140264607 Iii-v finfets on silicon substrate
09/18/2014US20140264606 Pixel structure
09/18/2014US20140264605 Hybrid ETSOI Structure to Minimize Noise Coupling from TSV
09/18/2014US20140264604 FinFET Having Source-Drain Sidewall Spacers with Reduced Heights
09/18/2014US20140264602 Forming strained and relaxed silicon and silicon germanium fins on the same wafer
09/18/2014US20140264600 FORMATION OF BULK SiGe FIN WITH DIELECTRIC ISOLATION BY ANODIZATION
09/18/2014US20140264599 Semiconductor device having reduced leakage current at breakdown and method of fabricating thereof
09/18/2014US20140264598 Stress enhanced finfet devices
09/18/2014US20140264596 Partially isolated fin-shaped field effect transistors
09/18/2014US20140264595 Forming strained and relaxed silicon and silicon germanium fins on the same wafer
09/18/2014US20140264594 FORMATION OF BULK SiGe FIN WITH DIELECTRIC ISOLATION BY ANODIZATION
09/18/2014US20140264593 Hybrid ETSOI Structure to Minimize Noise Coupling from TSV
09/18/2014US20140264592 Barrier Layer for FinFET Channels
09/18/2014US20140264591 Method and structure for dielectric isolation in a fin field effect transistor
09/18/2014US20140264590 FinFET with Bottom SiGe Layer in Source/Drain
09/18/2014US20140264589 Semiconductor structure profile
09/18/2014US20140264588 Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) with Step Oxide
09/18/2014US20140264587 Laterally diffused metal oxide semiconductor and method for fabricating the same
09/18/2014US20140264586 Bootstrap fet and method of manufacturing the same
09/18/2014US20140264585 Semiconductor device including lateral double diffused metal oxide semiconductor
09/18/2014US20140264584 Lateral double-diffused high voltage device
09/18/2014US20140264583 High-voltage semiconductor device
09/18/2014US20140264582 800 v superjunction device
09/18/2014US20140264581 Low on resistance semiconductor device
09/18/2014US20140264580 Semiconductor Device, Integrated Circuit and Method of Manufacturing a Semiconductor Device
09/18/2014US20140264579 Field Effect Transistor Devices with Buried Well Regions and Epitaxial Layers
09/18/2014US20140264578 Switch circuit using ldmos device
09/18/2014US20140264576 Integration of low rdson ldmos with high sheet resistance poly resistor
09/18/2014US20140264575 Mechanisms for doping lightly-doped-drain (ldd) regions of finfet devices
09/18/2014US20140264574 Electronic device including vertical conductive regions and a process of forming the same
09/18/2014US20140264573 Method for forming accumulation-mode field effect transistor with improved current capability
09/18/2014US20140264572 Methods of forming semiconductor devices using hard mask layers
09/18/2014US20140264571 Shielded gate trench mosfet package
09/18/2014US20140264570 Semiconductor device and method for forming the same
09/18/2014US20140264569 Methods and apparatus related to termination regions of a semiconductor device
09/18/2014US20140264568 Semiconductor device and methods of manufacturing the same
09/18/2014US20140264567 Direct-drain trench fet with source and drain isolation
09/18/2014US20140264566 Semiconductor element and manufacturing method and operating method of the same
09/18/2014US20140264565 Method of forming a transistor and structure therefor
09/18/2014US20140264564 Field Effect Transistor Devices with Buried Well Protection Regions
09/18/2014US20140264563 Field Effect Transistor Devices with Protective Regions
09/18/2014US20140264562 Field Effect Transistor Devices with Regrown P-Layers
09/18/2014US20140264561 Semiconductor device
09/18/2014US20140264560 Semiconductor device
09/18/2014US20140264559 Super junction trench metal oxide semiconductor device and method of making the same
09/18/2014US20140264558 Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels
09/18/2014US20140264557 Self-aligned approach for drain diffusion in field effect transistors
09/18/2014US20140264555 Silicon on germanium
09/18/2014US20140264554 Back-gated non-volatile memory cell
09/18/2014US20140264553 Method of fabricating monos semiconductor device
09/18/2014US20140264552 Nonvolatile memory cells and methods of making such cells
09/18/2014US20140264551 Memory transistor with multiple charge storing layers and a high work function gate electrode
09/18/2014US20140264550 Nonvolatile Charge Trap Memory Device Having a Deuterated Layer in a Multi-Layer Charge-Trapping Region
09/18/2014US20140264547 Nonvolatile semiconductor memory device and method of manufacturing the same
09/18/2014US20140264546 Damascene conductor for 3d array
09/18/2014US20140264544 Semiconductor device and methods of manufacturing
09/18/2014US20140264543 Structure and manufacturing method of a non-voltaile memory
09/18/2014US20140264542 Memory including blocking dielectric in etch stop tier
09/18/2014US20140264541 Structure and Method for Manufacture of Memory Device With Thin Silicon Body
09/18/2014US20140264540 Scalable and reliable non-volatile memory cell
09/18/2014US20140264538 Semiconductor devices and methods of manufacturing the same
09/18/2014US20140264537 Nonvolatile semiconductor storage device and method of manufacturing the same
09/18/2014US20140264535 Method for manufacturing semiconductor memory device and semiconductor memory device
09/18/2014US20140264534 Architecture to improve cell size for compact array of split gate flash cell
09/18/2014US20140264532 Floating gate memory cells in vertical memory
09/18/2014US20140264531 Nonvolatile semiconductor memory
09/18/2014US20140264530 Non-volatile Memory Cell Having A Trapping Charge Layer In A Trench And An Array And A Method Of Manufacturing Therefor
09/18/2014US20140264529 Semiconductor memory devices
09/18/2014US20140264528 Non-volatile memory structure
09/18/2014US20140264527 Local buried channel dielectric for vertical nand performance enhancement and vertical scaling
09/18/2014US20140264526 Gettering agents in memory charge storage structures
09/18/2014US20140264524 3d semiconductor structure and manufacturing method thereof
09/18/2014US20140264515 Ferroelectric field-effect transistor
09/18/2014US20140264499 Semiconductor devices having dielectric caps on contacts and related fabrication methods
09/18/2014US20140264498 Memory device and method of manufacturing the same
09/18/2014US20140264497 Self-aligned approach for drain diffusion in field effect transistors
09/18/2014US20140264496 Stress enhanced finfet devices
09/18/2014US20140264495 Self-aligned liner method of avoiding pl gate damage
09/18/2014US20140264494 Metal-Oxide-Semiconductor Field-Effect Transistor with Metal-Insulator Semiconductor Contact Structure to Reduce Schottky Barrier
09/18/2014US20140264493 Semiconductor Device and Fabricating the Same
09/18/2014US20140264492 Counter-doped low-power finfet
09/18/2014US20140264491 Semiconductor Strips with Undercuts and Methods for Forming the Same
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