Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
07/2003
07/23/2003CN1431714A Semi-conductor device and its mfg. method
07/23/2003CN1431711A Mutually compensating metal oxide semiconductor thin film transistor and its mfg. method
07/23/2003CN1431710A 半导体装置 Semiconductor device
07/23/2003CN1431549A Electrooptic appts. and electronic appliance
07/23/2003CN1115729C Semiconductor device and method for mfg. same
07/23/2003CN1115728C Monochip integrated circuit and method of fabricating monolithic integrated circuit
07/23/2003CN1115720C Method for mfg. semiconductor integrated circuit device
07/22/2003US6597415 Thin film transistor substrates for liquid crystal displays including thinner passivation layer on storage capacitor electrode than other regions
07/22/2003US6597349 Semiconductor display device and method of driving the same
07/22/2003US6597121 Active matrix organic EL display device and method of forming the same
07/22/2003US6597052 Punch-through diode having an inverted structure
07/22/2003US6597050 Method of contacting a silicide-based schottky diode and diode so formed
07/22/2003US6597045 Semiconductor raised source-drain structure
07/22/2003US6597044 Semiconductor device having a charge removal facility for minority carriers
07/22/2003US6597043 Narrow high performance MOSFET device design
07/22/2003US6597040 Semiconductor device having MOS transistor for coupling two signal lines
07/22/2003US6597038 MOS transistor with double drain structure for suppressing short channel effect
07/22/2003US6597036 Multi-value single electron memory using double-quantum dot and driving method thereof
07/22/2003US6597034 Non-volatile memory and semiconductor device
07/22/2003US6597026 Semiconductor device comprising plural isolated channels in a shallow trench isolation region
07/22/2003US6597021 Protection circuit and semiconductor device
07/22/2003US6597016 Semiconductor device and method for fabricating the same
07/22/2003US6597015 Multilayer; overcoating dielectric substrate; intake and drain zones
07/22/2003US6597014 Semiconductor device and semiconductor display device
07/22/2003US6597011 Dual non-parallel electronic field electro-optic effect device
07/22/2003US6597010 Solid-state quantum dot devices and quantum computing using nanostructured logic gates
07/22/2003US6596935 Chromophores absorb light and exhibit intrinsic molecular level rectification in the flow of excited-state energy and ground-state holes
07/22/2003US6596650 Method for fabricating semiconductor integrated circuit device
07/22/2003US6596648 Material removal method for forming a structure
07/22/2003US6596642 Material removal method for forming a structure
07/22/2003US6596636 ALD method to improve surface coverage
07/22/2003US6596617 CMOS compatible process for making a tunable negative differential resistance (NDR) device
07/22/2003US6596616 Method for forming serrated contact opening in the semiconductor device
07/22/2003US6596615 Semiconductor device and method of manufacturing the same
07/22/2003US6596612 Method for manufacturing semiconductor circuit
07/22/2003US6596608 Method of manufacturing non-volatile semiconductor memory device
07/22/2003US6596606 Semiconductor raised source-drain structure
07/22/2003US6596605 Method of forming germanium doped polycrystalline silicon gate of MOS transistor and method of forming CMOS transistor device using the same
07/22/2003US6596599 Gate stack for high performance sub-micron CMOS devices
07/22/2003US6596598 T-shaped gate device and method for making
07/22/2003US6596597 Method of manufacturing dual gate logic devices
07/22/2003US6596596 Methods of forming a field effect transistors
07/22/2003US6596595 Forming a conductive structure in a semiconductor device
07/22/2003US6596594 Method for fabricating field effect transistor (FET) device with asymmetric channel region and asymmetric source and drain regions
07/22/2003US6596590 Method of making multi-level type non-volatile semiconductor memory device
07/22/2003US6596589 Method of manufacturing a high coupling ratio stacked gate flash memory with an HSG-SI layer
07/22/2003US6596588 Method of fabricating a flash memory cell
07/22/2003US6596587 Shallow junction EEPROM device and process for fabricating the device
07/22/2003US6596585 Method of manufacturing semiconductor device
07/22/2003US6596576 Limiting hydrogen ion diffusion using multiple layers of SiO2 and Si3N4
07/22/2003US6596575 High voltage breakdown isolation semiconductor device and manufacturing process for making the device
07/22/2003US6596573 Thin film transistor including polycrystalline active layer and method for fabricating the same
07/22/2003US6596572 Method of fabricating a thin-film transistor having a plurality of island-like regions
07/22/2003US6596571 Method of manufacturing semiconductor device
07/22/2003US6596570 SOI device with reduced junction capacitance
07/22/2003US6596568 Thin film transistor and fabricating method thereof
07/22/2003US6596567 Method for fabricating a semiconductor device having a impurity layer disposed between a non-doped silicon film and high melting-point metal film for reducing solid state reaction between said high melting-point metal film and polycrystal silicon film
07/22/2003US6596555 Forming of quantum dots
07/22/2003US6596554 Body-tied-to-source partially depleted SOI MOSFET
07/22/2003US6595067 Pressure sensor using resin adhesive between sensor element and stem
07/22/2003US6595056 Micromachined silicon gyro using tuned accelerometer
07/17/2003WO2003058810A1 Encapsulated component which is small in terms of height and method for producing the same
07/17/2003WO2003058728A1 Electroluminescent device
07/17/2003WO2003058724A1 A thin film transistor array panel and a method for manufacturing the same
07/17/2003WO2003058723A1 Organic thin-film transistor and manufacturing method thereof
07/17/2003WO2003058722A1 High voltage power mosfet includes doped columns
07/17/2003WO2003058721A1 Organic semiconductor and method
07/17/2003WO2003058710A1 Method and structure for a heterojunction bipolar transistor
07/17/2003WO2003058702A1 Multiple conductive plug structure for lateral rf mos devices
07/17/2003WO2003058701A2 Uv-enhanced oxy-nitridation of semiconductor substrates
07/17/2003WO2003058695A1 Preparation of stack high-k gate dielectrics with nitrided layer
07/17/2003WO2003058693A2 Method for producing a capacitor
07/17/2003WO2003058684A2 High voltage power mosfet having a voltage sustaining region and diffusion from regions of oppositely doped polysilicon
07/17/2003WO2003058683A2 Method for fabricating a high voltage power mosfet having a voltage sustaining region that includes doped columns formed by rapid diffusion
07/17/2003WO2003058682A2 A METHOD FOR FORMING A POWER SEMICONDUCTOR AS IN FIGURE 5 HAVING A SUBSTRATE (2), A VOLTAGE SUSTAINING EPITAXIAL LAYER (1) WITH AT LEAST A TRENCH (52), A DOPED REGION (5a) ADJACENT AND SURROUNDING THE TRENCH.
07/17/2003WO2003058644A2 Superhard dielectric compounds and methods of preparation
07/17/2003WO2003058332A1 Reflection type liquid crystal display device and method of manufacturing the same
07/17/2003WO2003058258A1 Contactless acceleration switch
07/17/2003US20030134750 In a multiply-twisted helix including having a hierarchical structure in which a linear structure as an element of a the spiral structure of the lowest layer being N, the interval of bonds between m-th degree layers in the multiply-twisted helix
07/17/2003US20030134519 Thin film device provided with coating film, liquid crystal panel and electronic device, and method for making the thin film device
07/17/2003US20030134517 Semiconductor device and method for fabricating the same
07/17/2003US20030134514 Method of manufacturing nano transistors
07/17/2003US20030134506 Plasma display panel having trench discharge cell and method of fabricating the same
07/17/2003US20030134494 Compound semiconductor device and manufacturing method thereof
07/17/2003US20030134487 Method of forming a planar polymer transistor using substrate bonding techniques
07/17/2003US20030134486 Semiconductor-on-insulator comprising integrated circuitry
07/17/2003US20030134482 Ion-implantation and shallow etching to produce effective edge termination in high-voltage heterojunction bipolar transistors
07/17/2003US20030134480 Semiconductor device reducing junction leakage current and narrow width effect
07/17/2003US20030134479 Eliminating substrate noise by an electrically isolated high-voltage I/O transistor
07/17/2003US20030134476 Oxide-nitride-oxide structure
07/17/2003US20030134475 Method for manufacturing a multi-bit memory cell
07/17/2003US20030134474 Low voltage programmable and erasable flash EEPROM
07/17/2003US20030134472 Method of manufacturing a flash memory cell
07/17/2003US20030134468 Aggressive capacitor array cell layout for narrow diameter DRAM trench capacitor structures via SOI technology
07/17/2003US20030134464 Semiconductor device and method for the manufacture thereof
07/17/2003US20030134460 Active matrix thin film transistor array backplane
07/17/2003US20030134459 Semiconductor device and manufacturing method thereof
07/17/2003US20030134450 Elimination of RDL using tape base flip chip on flex for die stacking
07/17/2003US20030134438 Rare earth metal oxide memory element based on charge storage and method for manufacturing same
07/17/2003US20030134435 Multiple etch method for fabricating split gate field effect transistor (FET) device
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