Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
05/2005
05/19/2005US20050104138 Semiconductor device and manufacturing method thereof
05/19/2005US20050104137 Insulated gate field-effect transistor having III-VI source/drain layer(s)
05/19/2005US20050104135 Semiconductor device and manufacturing method thereof
05/19/2005US20050104134 Semiconductor device and method for manufacturing semiconductor device
05/19/2005US20050104131 Silicon device on Si:C-OI and SGOI and method of manufacture
05/19/2005US20050104130 High-density split-gate FinFET
05/19/2005US20050104128 Channel-etch thin film transistor
05/19/2005US20050104127 Bipolar transistor, BiCMOS device, and method for fabricating thereof
05/19/2005US20050104126 Semiconductor device and method for manufacturing semiconductor device
05/19/2005US20050104124 Semiconductor device
05/19/2005US20050104123 High voltage transistor
05/19/2005US20050104121 Method of fabricating a high-voltage transistor with an extended drain structure
05/19/2005US20050104119 Floating-gate semiconductor structures
05/19/2005US20050104118 Floating-gate semiconductor structures
05/19/2005US20050104117 Charge-trapping memory device and methods for operating and manufacturing the cell
05/19/2005US20050104116 Stacked gate memory cell with erase to gate, array, and method of manufacturing
05/19/2005US20050104115 Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby
05/19/2005US20050104114 Method for forming polysilicon local interconnects
05/19/2005US20050104112 Method of depositing barrier layer from metal gates
05/19/2005US20050104111 DRAM constructions, memory arrays and semiconductor constructions
05/19/2005US20050104106 Ferroelectric polymer memory with a thick interface layer
05/19/2005US20050104102 Magnetic storage device comprising memory cells including magneto-resistive elements
05/19/2005US20050104101 Spin-current switched magnetic memory element suitable for circuit integration and method of fabricating the memory element
05/19/2005US20050104099 Radiation-hardened transistor fabricated by modified CMOS process
05/19/2005US20050104098 Method of manufacturing a semiconductor device
05/19/2005US20050104097 Organic semiconductor transistor element, semiconductor device using the same, and process for producing the semiconductor device
05/19/2005US20050104096 FinFETs having first and second gates of different resistivities, and methods of fabricating the same
05/19/2005US20050104095 Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance
05/19/2005US20050104093 Semiconductor device and method for fabricating the same
05/19/2005US20050104092 Method of reducing dislocation-induced leakage in a strained-layer field-effect transistor
05/19/2005US20050104091 Self aligned damascene gate
05/19/2005US20050104089 Visible/near infrared image sensor
05/19/2005US20050104088 Semiconductor device
05/19/2005US20050104087 InGaP pHEMT device for power amplifier operation over wide temperature range
05/19/2005US20050104086 Optical receiver
05/19/2005US20050104082 Nitride semiconductor substrate and its production method
05/19/2005US20050104080 Semiconductor element and manufacturing method for the same
05/19/2005US20050104079 Encapsulated organic luminescent display panel and method for manufacturing the same
05/19/2005US20050104073 Solid-state display with improved color-mixing
05/19/2005US20050104070 Lower substrate, display apparatus having the same and method of manufacturing the same
05/19/2005US20050104069 Thin film transistor array panel and manufacturing method thereof
05/19/2005US20050104068 Method of fabricating a semiconductor device
05/19/2005US20050104067 Layer transfer of low defect SiGe using an etch-back process
05/19/2005US20050104066 Method of manufacturing substrate for electro-optical device, substrate for electro-optical device, electro-optical device, and electronic apparatus
05/19/2005US20050104065 Semiconductor device and method for forming the same
05/19/2005US20050104064 Semiconductor photodetector
05/19/2005US20050104062 Sub-nanoscale electronic devices and processes
05/19/2005US20050104061 Organic light emitting element, display apparatus having the same and method of manufacturing the same
05/19/2005US20050104060 Silicon particles as additives for improving charge carrier mobility in organic semiconductors
05/19/2005US20050104058 Organic field effect transistor with an organic dielectric
05/19/2005US20050104057 Methods of manufacturing a stressed MOS transistor structure
05/19/2005US20050104056 Electronic device using carbon element linear structure and production method thereof
05/19/2005US20050104055 Transistor of semiconductor device, and method for manufacturing the same
05/19/2005DE19840984B4 Halbleiterbauelement für integrierte Schaltkreise sowie Verfahren zur Herstellung A semiconductor device for integrated circuits and methods for preparing
05/19/2005DE19704995B4 Integrierte Hochspannungs-Leistungsschaltung Integrated high-voltage power circuit
05/19/2005DE19651109B4 Halbleitervorrichtung Semiconductor device
05/19/2005DE19603450B4 Halbleitervorrichtung mit einer Polyzidstruktur und Verfahren zur Herstellung derselben A semiconductor device having a polycide structure and method of manufacturing the same
05/19/2005DE10358985B3 Semiconductor element e.g. power semiconductor switch, with pn-junction and passivation layer at surface of semiconductor body acting as screening layer for edge structure limitation
05/19/2005DE10346460A1 Fuse/anti-fuse protection on chips, comprises a pacifying layer, a dielectric that covers it, and a redistribution layer
05/19/2005DE10344592A1 Adjustment method for a thyristor's reverse breakdown voltage uses negative- and positive-doped bases, a collector and an emitter along with hydrogen-induced donors
05/19/2005DE10344388A1 Verfahren zur Beseitigung der Auswirkungen von Defekten auf Wafern Method to remove the effects of defects on wafers
05/19/2005DE10297679T5 Dotierverfahren für vollständig verarmte SOI-Strukturen und Bauteil, das die resultierenden dotierten Gebiete enthält Doping method for fully depleted SOI-structures and components containing the resulting doped regions
05/19/2005DE102004050507A1 Piezoelektrischer Dünnfilmresonator und diesen nutzendes Filter A piezoelectric thin film resonator and filter-use these
05/19/2005DE102004043855A1 Verfahren zur Herstellung einer Magnet-Tunnel-Junction-Vorrichtung A method of manufacturing a magnetic tunnel junction device
05/19/2005CA2544854A1 Laser-based termination of passive electronic components
05/18/2005EP1531502A2 Super-thin oled and method for manufacturing the same
05/18/2005EP1531497A1 IGBT cathode design with improved safe operating area capability
05/18/2005EP1531496A2 Semiconductor devices having transistors and method for manufacturing the same
05/18/2005EP1531493A2 Flash memory array
05/18/2005EP1531491A2 SiC device and method for manufacturing the same
05/18/2005EP1531489A2 Wafer, semiconductor device, and fabrication methods therefor
05/18/2005EP1531155A1 Asymmetrical linear organic oligomers
05/18/2005EP1530803A2 Nrom memory cell, memory array, related devices an methods
05/18/2005EP1348110B1 Forming a composite pressure diaphragm with implantations, epitaxy, and a silicon nitride layer
05/18/2005EP1280101B1 Method of manufacturing cof package
05/18/2005CN2701075Y Separate pushing type double rectifier bridge
05/18/2005CN1618136A Self-aligned printing
05/18/2005CN1618131A Gas specie electron-jump chemical energy converter
05/18/2005CN1618130A Semiconductor device and its producing method
05/18/2005CN1618129A Negative differential resistance field effect transistor (NDR-FET) and circuits using the same
05/18/2005CN1618122A An oxide layer on a GAAS-based semiconductor structure and method of forming same
05/18/2005CN1618106A Memory cell utilizing negative differential resistance field-effect transistors
05/18/2005CN1618037A Amorphous silicon thin film transistor-liquid crystal display device and method of manufacturing the same
05/18/2005CN1617954A Deposition method for nanostructure materials
05/18/2005CN1617641A Super-thin OLED and method for manufacturing the same
05/18/2005CN1617367A Organic thin film transistor enhanced in charge carrier mobility by virtue of surface relief structure
05/18/2005CN1617354A Silicon carbide semiconductor device with junction type field effect transistor and its producing method
05/18/2005CN1617353A Method of manufacturing a semiconductor device
05/18/2005CN1617352A Manufacturing method of semiconductor device
05/18/2005CN1617351A 半导体显示器件 The semiconductor display device
05/18/2005CN1617346A Semiconductor memory device and manufacturing method thereof
05/18/2005CN1617343A Semiconductor device having metal silicide layer on source/drain region and gate electrode and method of manufacturing the same
05/18/2005CN1617337A Capacitor of a semiconductor device and memory device using the same
05/18/2005CN1617325A Method for forming insulation film of semiconductor device and semiconductor device
05/18/2005CN1617324A Method of forming metal line in semiconductor device
05/18/2005CN1617314A Process for twicely forming silicide in active region of transistor
05/18/2005CN1617313A Double pole transistor structure design of low start voltage gallium arsenide base new structure hetero junction
05/18/2005CN1617304A Method and structure to use an etch resistant liner on transistor gate structure
05/18/2005CN1617300A Fabrication method for polycrystalline silicon thin film and display device fabricated using the same
05/18/2005CN1617194A Improved LED array
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