Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
05/2005
05/19/2005WO2005046207A2 Image sensor with deep well region and method of fabricating the image sensor
05/19/2005WO2005045938A2 Insulated gate field-effect transistor
05/19/2005WO2005045937A2 Insulated gate field-effect transistor
05/19/2005WO2005045935A2 Sidewall formation for high density polymer memory element array
05/19/2005WO2005045924A1 An advanced technique for forming transistors having raised drain and source regions with different height
05/19/2005WO2005045918A1 Silicide formation for a semiconductor device
05/19/2005WO2005045901A2 METHOD AND STRUCTURE FOR FORMING STRAINED Si FOR CMOS DEVICES
05/19/2005WO2005045900A2 Method of fabricating a finfet
05/19/2005WO2005045896A2 Lateral high-voltage junction device
05/19/2005WO2005045892A2 Confined spacers for double gate transistor semiconductor fabrication process
05/19/2005WO2005045887A2 Method of forming an nmos transistor and structure thereof
05/19/2005WO2005045885A2 Anti-stiction technique for thin film and wafer-bonded encapsulated microelectromechanical systems
05/19/2005WO2005045797A1 Pixel circuit, display apparatus, and method for driving pixel circuit
05/19/2005WO2005045509A2 Electro-optic displays
05/19/2005WO2005027194A3 Method of making nonvolatile transistor pairs with shared control gate
05/19/2005WO2005020305A8 Optical device comprising crystalline semiconductor layer and reflective element
05/19/2005WO2005017975A3 Anchors for microelectromechanical systems having an soi substrate, and method of fabricating same
05/19/2005WO2005013281A3 Nonvolatile memory and method of making same
05/19/2005WO2004095526A3 Multi-bit non-volatile memory device and method therefor
05/19/2005WO2004093133A3 Silicon controlled rectifier electrostatic discharge protection device
05/19/2005WO2004093084A3 Mram architecture and a method and system for fabricating mram memories utilizing the architecture
05/19/2005US20050108676 Method for fabricating a liquid crystal display
05/19/2005US20050106898 Silicon nitride film and semiconductor device, and manufacturing method thereof
05/19/2005US20050106896 Processing apparatus and method
05/19/2005US20050106894 Semiconductor device and method for fabricating same
05/19/2005US20050106893 Surface preparation prior to deposition on germanium
05/19/2005US20050106850 Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETs
05/19/2005US20050106848 System and method for stress free conductor removal
05/19/2005US20050106847 Method of manufacturing semiconductor device and method of treating semiconductor surface
05/19/2005US20050106845 Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same
05/19/2005US20050106844 Method of fabricating a MOSFET device
05/19/2005US20050106843 Manufacturing method of semiconductor device
05/19/2005US20050106842 Method of forming a polysilicon layer comprising microcrystalline grains
05/19/2005US20050106837 Method for manufacturing a semiconductor device
05/19/2005US20050106833 Semiconductor device having metal silicide layer on source/drain region and gate electrode and method of manufacturing the same
05/19/2005US20050106829 Polysilicon bipolar transistor and method of manufacturing it
05/19/2005US20050106828 Switching regulator with high-side p-type device
05/19/2005US20050106825 Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor
05/19/2005US20050106823 MOSFET structure and method of fabricating the same
05/19/2005US20050106822 Method of manufacturing flash memory device
05/19/2005US20050106821 Transistor having high dielectric constant gate insulating layer and source and drain forming Schottky contact with substrate
05/19/2005US20050106816 Method of manufacturing a semiconductor memory device
05/19/2005US20050106815 Method for fabricating memory components
05/19/2005US20050106814 Method of manufacturing NAND flash device
05/19/2005US20050106813 Method of manufacturing flash memory device
05/19/2005US20050106812 Multi-bit non-volatile integrated circuit memory and method therefor
05/19/2005US20050106811 NROM flash memory devices on ultrathin silicon
05/19/2005US20050106806 Methods of forming a double-sided capacitor or a contact using a sacrificial structure
05/19/2005US20050106801 Method of manufacturing a semiconductor device having a silicide film
05/19/2005US20050106800 CMOS well structure and method of forming the same
05/19/2005US20050106798 Semiconductor device and method for fabricating the same
05/19/2005US20050106797 Encapsulated MOS transistor gate structures and methods for making the same
05/19/2005US20050106796 Method of forming ladder-type gate structure for four-terminal soi semiconductor device
05/19/2005US20050106793 Precision creation of inter-gates insulator
05/19/2005US20050106792 Transistor with strain-inducing structure in channel
05/19/2005US20050106791 Lateral double-diffused MOSFET
05/19/2005US20050106790 Strained silicon on a SiGe on SOI substrate
05/19/2005US20050106789 Method for producing an SOI field effect transistor and corresponding field effect transistor
05/19/2005US20050106787 Thin film transistor array substrate and method for manufacturing the same
05/19/2005US20050106771 Group III-V compound semiconductor and group III-V compound semiconductor device using the same
05/19/2005US20050106768 Active matrix substrate, method of manufacturing active matrix substrate, and intermediate transfer substrate for manufacturing active matrix substrate
05/19/2005US20050106765 Methods of testing/stressing a charge trapping device
05/19/2005US20050105869 Three-dimensional photonic crystal waveguide structure and method
05/19/2005US20050105361 Charge trapping memory cell and method for operating a charge trapping memory cell
05/19/2005US20050105353 Method for operating a memory cell array
05/19/2005US20050105341 NROM flash memory with self-aligned structural charge separation
05/19/2005US20050105339 Nonvolatile memory
05/19/2005US20050105336 Nonvolatile semiconductor memory
05/19/2005US20050105335 Semiconductor memory device and electric device with the same
05/19/2005US20050105330 Semiconductor memory device and manufacturing method thereof
05/19/2005US20050105317 Data processor including an authentication function for judging access right
05/19/2005US20050105233 Temperature protection device for power devices
05/19/2005US20050105034 Liquid crystal display device
05/19/2005US20050105032 Liquid crystal display device
05/19/2005US20050105031 [pixel structure of display and driving method thereof]
05/19/2005US20050105010 Liquid crystal display, thin film diode panel, and manufacturing method of the same
05/19/2005US20050104830 Method and device for measuring drive current of thin film transistor array
05/19/2005US20050104614 Inspection device for inspecting TFT
05/19/2005US20050104605 Sensor and electrode extraction structure and method
05/19/2005US20050104516 Super-thin OLED and method for manufacturing the same
05/19/2005US20050104229 Semiconductor device having align key and method of fabricating the same
05/19/2005US20050104227 Substrate-based package for integrated circuits
05/19/2005US20050104216 Electroplated CoWP composite structures as copper barrier layers
05/19/2005US20050104173 Semiconductor device and manufacturing method thereof
05/19/2005US20050104165 Semiconductor element, semiconductor device, and method for manufacturing semiconductor element
05/19/2005US20050104162 Vicinal gallium nitride substrate for high quality homoepitaxy
05/19/2005US20050104160 Bipolar junction transistor with improved extrinsic base region and method of fabrication
05/19/2005US20050104159 Power generator and method for forming same
05/19/2005US20050104155 Diode structure and integral power switching arrangement
05/19/2005US20050104154 Design implementation to suppress latchup in voltage tolerant circuits
05/19/2005US20050104153 Semiconductor device
05/19/2005US20050104152 Schottky barrier integrated circuit
05/19/2005US20050104150 Structure comprising tunable anti-reflective coating and method of forming thereof
05/19/2005US20050104146 Thin film device and a method of providing thermal assistance therein
05/19/2005US20050104144 Method and apparatus to reduce parasitic forces in electro-mechanical systems
05/19/2005US20050104143 Nonvolatile memory with undercut trapping structure
05/19/2005US20050104142 CVD tantalum compounds for FET get electrodes
05/19/2005US20050104141 Semiconductor device and process for producing the same
05/19/2005US20050104140 Low-power multiple-channel fully depleted quantum well CMOSFETs
05/19/2005US20050104139 Method of forming fet with T-shaped gate
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