Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
03/1990
03/20/1990US4910566 Layer structure of a memory cell for a dynamic random access memory device and method for producing the same
03/20/1990US4910565 Electrically erasable and electrically programmable read-only memory
03/20/1990US4910564 Highly integrated field effect transistor and method for manufacturing the same
03/20/1990US4910562 Field induced base transistor
03/20/1990US4910499 Tag and method of making same
03/20/1990US4910232 Ultraviolet-curable organopolysiloxane composition
03/20/1990US4910170 Forming grooves in film
03/20/1990US4910169 Forming copper metallization film; patterning; depositing dielectric
03/20/1990US4910168 Method to reduce silicon area for via formation
03/20/1990US4910167 III-V Semiconductor growth initiation on silicon using TMG and TEG
03/20/1990US4910165 Method for forming epitaxial silicon on insulator structures using oxidized porous silicon
03/20/1990US4910164 Forming masked recesses; deposit second layer; remove second layer; remove except over recesses
03/20/1990US4910163 Gaseous stream of iodine and carrier gas; passing through silicon to produce silicon iodide; disproportionate with silicon oxide; deposit silicon on substrate
03/20/1990US4910162 Integrated circuit; containing silicon switch transistor
03/20/1990US4910161 Preparing first electroconductive semiconductor substate; doping; forming electrodes; then second electroconductive layer; supplying constant voltage
03/20/1990US4910160 Masking oxide, etching, applying dopes, diffusion cycles on silicon substrate
03/20/1990US4910159 Forming a diffused p-type secondary collector region; joining to primary collector region
03/20/1990US4910157 Method of producing recessed gate of MESFET in compound semiconductor
03/20/1990US4910156 Doping phosphor into crystal
03/20/1990US4910155 Wafer flood polishing
03/20/1990US4910122 Anti-reflective coating
03/20/1990US4910094 Heating, diffusion, exposure
03/20/1990US4910043 Processing apparatus and method
03/20/1990US4909998 Apparatus for performing solution growth of group II-VI compound semiconductor crystal
03/20/1990US4909897 Local oxidation of silicon process
03/20/1990US4909863 Polishing intermetallic surface with aqueous solution containing bromine and an acid
03/20/1990US4909857 Doped intermetallic of tellurium and group 2b metal
03/20/1990US4909701 Articulated arm transfer device
03/20/1990US4909695 Method and apparatus for handling and processing wafer-like materials
03/20/1990US4909431 Method and apparatus for preparing a bonding wire
03/20/1990US4909428 Furnace to solder integrated circuit chips
03/20/1990US4909314 Apparatus for thermal treatment of a wafer in an evacuated environment
03/20/1990US4909184 Apparatus for the formation of a functional deposited film using microwave plasma chemical vapor deposition process
03/20/1990US4909183 Apparatus for plasma CVD
03/20/1990US4908937 Method to install an electronic component and its electrical connections on a support, and product obtained thereby
03/20/1990US4908935 Method for fabricating electronic devices
03/20/1990US4908933 Method of manufacturing a substrate for mounting electronic components
03/20/1990CA1266923A1 Ion beam implantation display method and apparatus
03/20/1990CA1266812A1 Method of fabricating a self-aligned metal- semiconductor fet
03/20/1990CA1266805A1 Semiconductor fabrication
03/15/1990DE3927679A1 Transistor with emitter layer diffused in base layers - has collector layer near base layer, but spaced from emitter layer with sectional main region
03/15/1990DE3913540A1 Self-adjusting Schottky gate formation - involves self-adjusting gate electrode mfr., using structural layer(s) for gate form mfr.
03/15/1990DE3831130A1 Method for producing semiconducting, thin layers on an insulating substrate
03/15/1990DE3830299A1 Method and arrangement for determining internal thermal resistances of wafer-shaped semiconductor components
03/15/1990DE3829906A1 Method for producing semiconductor components
03/15/1990DE3828378A1 Method for producing small openings in thin films
03/14/1990EP0358567A2 Method of exposing patterns of semiconductor devices and stencil mask for carrying out same
03/14/1990EP0358517A2 Compositions including a phenolic resin and a sensitizer
03/14/1990EP0358513A2 Position detecting method and apparatus
03/14/1990EP0358512A2 Position detecting method and apparatus
03/14/1990EP0358467A2 Exposure apparatus and control of the same
03/14/1990EP0358443A2 Mask cassette loading device
03/14/1990EP0358426A2 SOR exposure system
03/14/1990EP0358425A2 Position detecting method and apparatus
03/14/1990EP0358376A2 Integrated test circuit
03/14/1990EP0358371A2 Enhanced test circuit
03/14/1990EP0358365A2 Testing buffer/register
03/14/1990EP0358350A2 Forming a Prescribed Pattern on a Semiconductor Device Layer
03/14/1990EP0358246A1 Method of manufacturing a semiconductor device comprising a silicon body in which semiconductor regions are formed by ion implantations
03/14/1990EP0358194A2 Positive-type photoresist composition
03/14/1990EP0358077A2 Semiconductor device and method of forming it
03/14/1990EP0358042A2 Self-aligned process for manufacturing a gate electrode
03/14/1990EP0357982A2 Memory cell with improved single event upset rate reduction circuitry
03/14/1990EP0357980A2 A memory cell with capacitance for single event upset protection
03/14/1990EP0357824A1 A sheet plasma sputtering method and an apparatus for carrying out the method
03/14/1990EP0357802A1 Methods of manufacture of a resin-sealed semiconductor device
03/14/1990EP0357769A1 Vernier structure for flip chip bonded devices
03/14/1990EP0357759A1 Alignment of leads for ceramic integrated circuit packages
03/14/1990EP0357616A1 Process and device for compensating errors of measurement.
03/14/1990EP0357606A1 Low stress heat sinking for semiconductors
03/14/1990EP0160003B1 Mos floating gate memory cell and process for fabricating same
03/14/1990CN1040462A Cmos transistor and one-capacitor dynamic-random-access memory cell and fabrication process thereof
03/14/1990CN1040461A Electric device and mfg. method of same by use of plasma processing
03/14/1990CN1040460A Forming ways of silicon seperate structure using the oxidization of obstruction style porous silicon
03/14/1990CN1040401A Vapour-phase gaas/inp hetero epitaxial technique
03/13/1990US4908871 Pattern inspection system
03/13/1990US4908736 Self packaging chip mount
03/13/1990US4908696 Connector and semiconductor device packages employing the same
03/13/1990US4908692 Fuse-containing semiconductor device
03/13/1990US4908691 Selective epitaxial growth structure and isolation
03/13/1990US4908690 Semiconductor integrated circuit device with high reliability wiring layers
03/13/1990US4908689 Organic solder barrier
03/13/1990US4908688 Means and method for providing contact separation in silicided devices
03/13/1990US4908683 Technique for elimination of polysilicon stringers in direct moat field oxide structure
03/13/1990US4908680 Semiconductor integrated circuit
03/13/1990US4908679 Low resistance Schottky diode on polysilicon/metal-silicide
03/13/1990US4908495 For use with semiconductor reactors
03/13/1990US4908348 Barrier layer arrangement for conductive layers on silicon substrates
03/13/1990US4908334 Method for forming metallic silicide films on silicon substrates by ion beam deposition
03/13/1990US4908333 Process for manufacturing a semiconductor device having a contact window defined by an inclined surface of a composite film
03/13/1990US4908332 Process for making metal-polysilicon double-layered gate
03/13/1990US4908331 Method of manufacturing a semiconductor device by depositing metal on semiconductor maintained at temperature to form silicide
03/13/1990US4908329 Microwave plasma generated in plasma generation chamber in cavity resonator integrated with impedance circuits for film formation
03/13/1990US4908328 High voltage power IC process
03/13/1990US4908327 Counter-doped transistor
03/13/1990US4908326 Process for fabricating self-aligned silicide lightly doped drain MOS devices
03/13/1990US4908325 Forming gallium arsenide layer, forming doped epitaxial layer of aluminum gallium arsenide, growing aluminum arsenide layer, forming overlying layer, etching, depositing gate electrode
03/13/1990US4908324 Forming insulating film on semiconductor wafer, masking, patterning, depositing conductive material, masking, etching, doping, forming oxide film, doping
03/13/1990US4908299 Forming several layers of sensitive Langmuir-Blodgett film containing silicon, selectively polymerizing or decomposing by radiation, selectively etching
03/13/1990US4908226 Selective area nucleation and growth method for metal chemical vapor deposition using focused ion beams
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