Patents
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
06/2010
06/15/2010US7737419 Alignment apparatus, exposure apparatus, and device manufacturing method
06/15/2010US7737416 Sample transfer unit and sample transferring method
06/15/2010US7737385 Selective reflectivity process chamber with customized wavelength response and method
06/15/2010US7737055 Systems and methods for manipulating liquid films on semiconductor substrates
06/15/2010US7737054 Laser irradiation apparatus, laser irradiation method, and method for manufacturing a semiconductor device
06/15/2010US7737053 Semiconductor device and manufacturing method of the same
06/15/2010US7737052 Advanced multilayer dielectric cap with improved mechanical and electrical properties
06/15/2010US7737051 Silicon germanium surface layer for high-k dielectric integration
06/15/2010US7737050 Method of fabricating a nitrided silicon oxide gate dielectric layer
06/15/2010US7737049 Method for forming a structure on a substrate and device
06/15/2010US7737048 Method for controlling thickness distribution of a film
06/15/2010US7737047 Semiconductor constructions, and methods of forming dielectric materials
06/15/2010US7737046 Quantum dot array and production method therefor, and dot array element and production method therefor
06/15/2010US7737045 Microfabricated micro fluid channels
06/15/2010US7737044 Solid state imaging device, manufacturing method of the same, and substrate for solid state imaging device
06/15/2010US7737043 Inspection method of compound semiconductor substrate, compound semiconductor substrate, surface treatment method of compound semiconductor substrate, and method of producing compound semiconductor crystal
06/15/2010US7737042 Pulsed-plasma system for etching semiconductor structures
06/15/2010US7737041 Semiconductor device and method of manufacturing the same
06/15/2010US7737040 Method of reducing critical dimension bias during fabrication of a semiconductor device
06/15/2010US7737039 Spacer process for on pitch contacts and related structures
06/15/2010US7737038 Method of fabricating semiconductor device including planarizing conductive layer using parameters of pattern density and depth of trenches
06/15/2010US7737037 Semiconductor device and method of manufacturing the same
06/15/2010US7737036 Integrated circuit fabrication process with minimal post-laser annealing dopant deactivation
06/15/2010US7737035 Dual seal deposition process chamber and process
06/15/2010US7737034 Substrate treating apparatus and method for manufacturing semiconductor device
06/15/2010US7737033 Etchant and method for fabricating electric device including thin film transistor using the same
06/15/2010US7737032 MOSFET structure with multiple self-aligned silicide contacts
06/15/2010US7737031 Insitu formation of inverse floating gate poly structures
06/15/2010US7737030 Method for manufacturing a semiconductor device, and said semiconductor device
06/15/2010US7737029 Methods of forming metal interconnect structures on semiconductor substrates using oxygen-removing plasmas and interconnect structures formed thereby
06/15/2010US7737028 Selective ruthenium deposition on copper materials
06/15/2010US7737026 Structure and method for low resistance interconnections
06/15/2010US7737025 Via including multiple electrical paths
06/15/2010US7737024 Small grain size, conformal aluminum interconnects and method for their formation
06/15/2010US7737023 Method of manufacture of semiconductor integrated circuit device and semiconductor integrated circuit device
06/15/2010US7737022 Contact formation
06/15/2010US7737021 Resist trim process to define small openings in dielectric layers
06/15/2010US7737020 Method of fabricating CMOS devices using fluid-based dielectric materials
06/15/2010US7737019 Method for containing a silicided gate within a sidewall spacer in integrated circuit technology
06/15/2010US7737018 Process of forming an electronic device including forming a gate electrode layer and forming a patterned masking layer
06/15/2010US7737017 Semiconductor device having recess gate and isolation structure and method for fabricating the same
06/15/2010US7737016 Two-print two-etch method for enhancement of CD control using ghost poly
06/15/2010US7737015 Formation of fully silicided gate with oxide barrier on the source/drain silicide regions
06/15/2010US7737014 Reduction of boron diffusivity in pFETs
06/15/2010US7737013 Implantation of multiple species to address copper reliability
06/15/2010US7737012 Manufacturing method of a semiconductor device
06/15/2010US7737011 Method for improving the quality of an SiC crystal and an SiC semiconductor device
06/15/2010US7737010 Method of photoresist strip for plasma doping process of semiconductor manufacturing
06/15/2010US7737009 Method of implanting a non-dopant atom into a semiconductor device
06/15/2010US7737008 Method for making quantum dots
06/15/2010US7737007 Methods to fabricate MOSFET devices using a selective deposition process
06/15/2010US7737006 Methods and apparatus to form electronic components with at least one N- or P-doped portion
06/15/2010US7737005 Method for forming Ti film and TiN film, contact structure, computer readable storing medium and computer program
06/15/2010US7737004 Multilayer gettering structure for semiconductor device and method
06/15/2010US7737003 Method and structure for optimizing yield of 3-D chip manufacture
06/15/2010US7737002 Wafer dividing method
06/15/2010US7737001 Semiconductor manufacturing method
06/15/2010US7737000 Process for the collective fabrication of microstructures consisting of superposed elements
06/15/2010US7736999 Manufacturing method of semiconductor device
06/15/2010US7736998 Silicon-on insulator substrate and method for manufacturing the same
06/15/2010US7736997 Production method of flexible electronic device
06/15/2010US7736996 Method for damage avoidance in transferring an ultra-thin layer of crystalline material with high crystalline quality
06/15/2010US7736995 Process for producing components
06/15/2010US7736994 Method for manufacturing compound material wafers and corresponding compound material wafer
06/15/2010US7736993 Composite substrate and method of fabricating the same
06/15/2010US7736992 Isolation trench geometry for image sensors
06/15/2010US7736991 Method of forming isolation layer of semiconductor device
06/15/2010US7736990 Semiconductor device and manufacturing method for the same
06/15/2010US7736989 Method of forming semiconductor device
06/15/2010US7736988 Forming structures that include a relaxed or pseudo-relaxed layer on a substrate
06/15/2010US7736987 Methods of forming semiconductor constructions
06/15/2010US7736986 Integrated stacked capacitor and method of fabricating same
06/15/2010US7736985 Method for manufacturing semiconductor device using overlapping exposure and semiconductor device thereof
06/15/2010US7736984 Method of forming a low resistance semiconductor contact and structure therefor
06/15/2010US7736983 High threshold NMOS source-drain formation with As, P and C to reduce damage
06/15/2010US7736982 Method for forming a semiconductor device
06/15/2010US7736980 Vertical gated access transistor
06/15/2010US7736979 Method of forming nanotube vertical field effect transistor
06/15/2010US7736978 Method of manufacturing a trench transistor having a heavy body region
06/15/2010US7736977 Semiconductor device and a method for manufacturing therefor
06/15/2010US7736976 Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands
06/15/2010US7736975 Method for manufacturing non-volatile memory device having charge trap layer
06/15/2010US7736974 Method for manufacturing semiconductor device to prevent defects due to insulation layer volume change
06/15/2010US7736973 Non-volatile memory arrays having dual control gate cell structures and a thick control gate dielectric and methods of forming
06/15/2010US7736972 Method for forming storage electrode of semiconductor memory device
06/15/2010US7736971 Semiconductor device and method of fabricating the same
06/15/2010US7736970 Method of fabricating semiconductor device having capacitor
06/15/2010US7736969 DRAM layout with vertical FETS and method of formation
06/15/2010US7736968 Reducing poly-depletion through co-implanting carbon and nitrogen
06/15/2010US7736967 Method and structure of an one time programmable memory device in an embedded EEPROM
06/15/2010US7736966 CMOS devices with hybrid channel orientations and method for fabricating the same
06/15/2010US7736965 Method of making a FinFET device structure having dual metal and high-k gates
06/15/2010US7736964 Semiconductor device, and method for manufacturing the same
06/15/2010US7736963 Method of forming a gate structure for a semiconductor device and method of forming a cell gate structure for a non-volatile memory device
06/15/2010US7736962 Advanced JFET with reliable channel control and method of manufacture
06/15/2010US7736961 High voltage depletion FET employing a channel stopping implant
06/15/2010US7736960 Process for producing a photoelectric conversion device
06/15/2010US7736959 Integrated circuit device, and method of fabricating same
06/15/2010US7736958 Method for manufacturing semiconductor device
06/15/2010US7736957 Method of making a semiconductor device with embedded stressor