Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
Patents for H01L 21 - Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof (658,974)
07/2011
07/20/2011CN102130059A Method of forming an integrated circuit
07/20/2011CN102130058A CMOS (Complementary Metal Oxide Semiconductor) transistor and manufacturing method thereof
07/20/2011CN102130057A Method for making complementary metal oxide semiconductor device, and structure of complementary metal oxide semiconductor device
07/20/2011CN102130056A Method for producing complementary metal oxide semiconductor structure
07/20/2011CN102130055A Method for improving breakdown voltage of trench double gate MOS (Metal Oxide Semiconductor) device
07/20/2011CN102130054A Method for improving divergence of cut-off leakage current of semiconductor device
07/20/2011CN102130053A Method for making integrated amplifier of N-channel junction field effect transistor (JFET)
07/20/2011CN102130052A Back side illumination image sensor and a forming process thereof
07/20/2011CN102130051A Light-emitting diode and manufacturing method thereof
07/20/2011CN102130050A Multi-project wafer cutting method supporting constraint and limitation on positions of chips
07/20/2011CN102130049A Manufacturing method of semiconductor device and semiconductor device
07/20/2011CN102130048A Semiconductor die singulation method
07/20/2011CN102130047A Semiconductor die singulation method
07/20/2011CN102130046A Interfacial layers for electromigration resistance improvement in damascene interconnects
07/20/2011CN102130045A Through hole processing method
07/20/2011CN102130044A Method for forming insulating layer in silicon through hole
07/20/2011CN102130043A Method for filling redundancy metal
07/20/2011CN102130042A Method for manufacturing through hole interconnection structure
07/20/2011CN102130041A Semiconductor device and semiconductor technique thereof
07/20/2011CN102130040A Method for forming through-hole interconnection and metalizing contact of carbon nano tube
07/20/2011CN102130039A Method for preparing semiconductor substrate with insulated buried layer by adopting gettering process
07/20/2011CN102130038A Method for preparing silicon-on-insulator by ion implantation
07/20/2011CN102130037A Method for preparing semiconductor substrate with insulation buried layer by adopting gettering process
07/20/2011CN102130036A Method for producing shallow trench isolating structure
07/20/2011CN102130035A Integrated chip tray
07/20/2011CN102130034A Loadlock and loadlock chamber using the same
07/20/2011CN102130033A Workpiece support structures and apparatus for accessing same
07/20/2011CN102130032A Online detection method of ion implantation
07/20/2011CN102130031A Method for detecting wafer
07/20/2011CN102130030A Method for detecting mechanical scratching condition of silicon wafers
07/20/2011CN102130029A Method for detecting temperature distribution of furnace tube
07/20/2011CN102130028A Lower hot-pressing device on RFID (radio frequency identification) flip packaging device
07/20/2011CN102130027A 半导体器件 Semiconductor devices
07/20/2011CN102130026A Wafer-level low-temperature packaging method based on gold-tin alloy bonding
07/20/2011CN102130025A Wafer, processing method thereof and method for manufacturing semiconductor device
07/20/2011CN102130024A Method for plating silver on front side of silicon wafer
07/20/2011CN102130023A Method for forming aluminum cushion
07/20/2011CN102130022A Method of forming a semiconductor die
07/20/2011CN102130021A Silicon carbide power module and packaging method thereof
07/20/2011CN102130020A Method for packaging silicon carbide power device
07/20/2011CN102130019A Semiconductor packaging process and die utilized in same
07/20/2011CN102130018A Chip radiation method, and related device and system
07/20/2011CN102130017A Manufacturing method for composite substrate
07/20/2011CN102130016A Integrated circuit chip package substrate, device including the same and electronic device
07/20/2011CN102130015A Trench-gate vertical mosfet manufacturing method
07/20/2011CN102130014A Method for manufacturing FinFET (field effect transistor)
07/20/2011CN102130013A Method for manufacturing SOI (silicon on insulator) super junction LDMOS (lateral double-diffused metal oxide semiconductor) device with buffer layer
07/20/2011CN102130012A LDD, LDS and buffer layer integrated manufacturing method for SOI super-junction LDMOS device
07/20/2011CN102130011A Method for manufacturing transistor
07/20/2011CN102130010A Method of filling large deep trench with high quality oxide for semiconductor devices
07/20/2011CN102130009A Manufacturing method of transistor
07/20/2011CN102130008A Method for forming semiconductor fins
07/20/2011CN102130007A Preparation method of trench double gate power MOS (Metal Oxide Semiconductor) transistor
07/20/2011CN102130006A Method for preparing groove-type double-layer gate power metal oxide semiconductor (MOS) transistor
07/20/2011CN102130005A Preparation method of trench PMOS (positive-channel metal oxide semiconductor) enabling side wall of trench to be (110) surface
07/20/2011CN102130004A Preparation method of trench type MOS (metal oxide semiconductor) device
07/20/2011CN102130003A Preparation method of vertical trench MOS (Metal Oxide Semiconductor) device
07/20/2011CN102130002A Method for preparing longitudinal trench type MOS (metal oxide semiconductor) device
07/20/2011CN102130001A Preparation method of trench double gate power MOS (Metal Oxide Semiconductor) device
07/20/2011CN102130000A Method for preparing channel-type double-gate MOS device
07/20/2011CN102129999A Method for producing groove type dual-layer grid MOS (Metal Oxide Semiconductor) structure
07/20/2011CN102129998A Method for forming polysilicon P type column in N type super-junction VDMOS (Vertical Double Diffused Metal Oxide Semiconductor)
07/20/2011CN102129997A Method for forming P-type pole in N-type super junction vertical double diffused metal oxide semiconductor (VDMOS)
07/20/2011CN102129996A Manufacturing method of DDDMOS (Double Diffused Drain MOS (Metal-Oxide-Semiconductor)) device
07/20/2011CN102129995A Method for forming metal silicide contact layer and field effect transistor
07/20/2011CN102129994A Method of manufacturing heterojunction bipolar transistor and heterojunction bipolar transistor
07/20/2011CN102129993A Method for manufacturing oxide layer/ nitride layer/ oxide layer side wall
07/20/2011CN102129992A Method for improving impurity concentration distribution of impurity injection type polysilicon emitter
07/20/2011CN102129991A Method for improving diagram forming of emitting electrode window in SiGe process
07/20/2011CN102129990A Method for manufacturing base region of bipolar transistor
07/20/2011CN102129989A Method for manufacturing surface electric field-shielded Schottky diode chip
07/20/2011CN102129988A Manufacturing method of low-capacitance Schottky diode
07/20/2011CN102129987A Process for passivating bidirectional trigger diode scrapped glass
07/20/2011CN102129986A Method for manufacturing glass sealed diode by adopting metallurgy bonding method
07/20/2011CN102129985A Manufacturing method of glass-sealed two-way trigger diode chip
07/20/2011CN102129984A Dry etching method of silicon compound film
07/20/2011CN102129983A Etching method and etching apparatus
07/20/2011CN102129982A Manufacturing method of fine pattern of semiconductor and FIN body of fin type field effect transistor
07/20/2011CN102129981A Manufacturing methods of nanowire and nanowire transistor
07/20/2011CN102129980A Semiconductor device with buried gate electrodes and forming method thereof
07/20/2011CN102129979A Semiconductor device and its manufacture method
07/20/2011CN102129978A Method of forming a metal gate
07/20/2011CN102129977A High-resistance resistor and method for realizing same
07/20/2011CN102129976A Floating gates of EEPROM (electrically erasable programmable read-only memory) and manufacturing method thereof
07/20/2011CN102129975A Method for forming metal gate by plasma etching process
07/20/2011CN102129974A Method for etching unit grid
07/20/2011CN102129973A Ion implanter turntable and cleaning method thereof
07/20/2011CN102129972A Method for dispersing power chip with low power consumption and deeper junction
07/20/2011CN102129971A Method and system for etching graphical sapphire substrate
07/20/2011CN102129970A Method for manufacturing semiconductor device
07/20/2011CN102129969A Method of forming an em protected semiconductor die
07/20/2011CN102129968A Double-patterning method
07/20/2011CN102129967A Nitride semiconductor template and method of manufacturing the same
07/20/2011CN102129966A Methods of forming a thermal conduction region in a semiconductor structure and structures resulting therefrom
07/20/2011CN102129965A Thin film resistor
07/20/2011CN102129964A Method for manufacturing resistor end effect curves of thick-film integrated circuit
07/20/2011CN102129963A Dual-arm mechanical arm and method for moving plates by using same
07/20/2011CN102129962A Controllable method for manufacturing polysilicon thin film through metal induction
07/20/2011CN102129961A Manufacturing method of chip label
07/20/2011CN102129960A Method for producing capacitor
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