Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
05/2008
05/08/2008US20080106931 Phase change memory device
05/08/2008US20080106930 Pram and method of firing memory cells
05/08/2008US20080106928 Energy adjusted write pulses in phase-change memory cells
05/08/2008DE19807014B4 Halbleiterspeicherelement mit verbesserter Datenausgabegeschwindigkeit The semiconductor memory device with improved data output rate
05/08/2008DE102007047377A1 Speicherzugriff-Strobe-Konfigurationssystem und -verfahren Memory access strobe configuration system and method
05/08/2008DE102006054554A1 Speichereinrichtung-Architektur und Verfahren zum Vorladen einer Bitleitung mit hoher Geschwindigkeit Memory device architecture and method for precharging a bit line at high speed
05/08/2008DE102006052338A1 Memory unit i.e. dynamic RAM, operating method, involves producing read connection between memory area and output buffer at time interval after providing read instruction for transferring read information from memory area to output buffer
05/08/2008DE102006051514A1 Speichermodul und Verfahren zum Betreiben eines Speichermoduls Memory module and method of operating a memory module
05/08/2008DE102006051136A1 Adapter card for use with memory module system i.e. fully buffered-dual in-line memory module system, has memory plug contact for connecting adapter card to memory module e.g. unregistered dual in-line memory module
05/08/2008DE102006050362A1 Synchronisationsvorrichtung und Verfahren zur Datensynchronisation Synchronization apparatus and method for data synchronization
05/08/2008DE102006049310A1 Digital registered data buffer for use in RAM memory system, has clock output of phase-locked loop providing clock signal shifted in phase by specific degree plus fraction of clock period with respect to feedback clock signal
05/08/2008DE102005053496B4 Speicherbauelement mit mehreren resistiv schaltenden Speicherzellen, insbesondere PCM-Speicherzellen Memory device having a plurality of resistive switching memory cells, in particular PCM memory cells
05/08/2008DE10059513B4 Verfahren und Schaltungsanordnung zum Ansteuern eines Datentreibers Method and circuit for controlling a data driver
05/07/2008EP1919120A1 Data/strobe encoding scheme circuit and data/strobe encoding method
05/07/2008EP1917313A1 Red-shifted water-dispersible naphthalocyanine dyes
05/07/2008CN101176160A Identical chips with different operations in a system
05/07/2008CN101176159A Method to handle write mask in DRAM memory
05/07/2008CN101174818A Method and device for playing media file
05/07/2008CN101174454A MP3 player flickering with music
05/07/2008CN101174453A Equalizer circuit and method of controlling the same
05/07/2008CN101174452A Memory module and method for operating a memory module
05/07/2008CN100386822C Method for testing a memory device
05/07/2008CN100386819C Data output buffer capable of controlling data valid window in semiconductor memory devices
05/07/2008CN100386818C Low power hynamic RAM with bit line pre-charge, inversion data write and storing data output
05/07/2008CN100386713C Method and apparatus for controlling a user interface of a consumer electronic device
05/06/2008US7370170 Data mask as write-training feedback flag
05/06/2008US7370168 Memory card conforming to a multiple operation standards
05/06/2008US7370140 Enhanced DRAM with embedded registers
05/06/2008US7370134 System and method for memory hub-based expansion bus
05/06/2008US7369855 Methods and apparatus for the utilization of core based nodes for state transfer
05/06/2008US7369456 DRAM memory with autoprecharge
05/06/2008US7369451 Dynamic random access memory device and method for self-refreshing memory cells
05/06/2008US7369450 Nonvolatile memory having latching sense amplifier and method of operation
05/06/2008US7369449 Semiconductor integrated circuit and data output method
05/06/2008US7369448 Input circuit for memory device
05/06/2008US7369447 Random cache read
05/06/2008US7369446 Method and apparatus to prevent high voltage supply degradation for high-voltage latches of a non-volatile memory
05/06/2008US7369445 Methods of operating memory systems including memory devices set to different operating modes and related systems
05/06/2008US7369444 Early read after write operation memory device, system and method
05/06/2008US7369443 Semiconductor device with adjustable signal drive power
05/06/2008US7368965 Clock capture in clock synchronization circuitry
05/06/2008US7368953 Buffer
05/06/2008US7368937 Input termination circuits and methods for terminating inputs
05/02/2008WO2008052130A1 Memory device with configurable delay tracking
05/02/2008WO2008051467A1 Skew management in an interconnection system
05/02/2008WO2008016950A3 Method and apparatus for memory array incorporating two data busses for memory array block selection
05/01/2008US20080104376 Method and Apparatus for Performing Group Instructions
05/01/2008US20080101526 Phase Controlled High Speed Interfaces
05/01/2008US20080101144 High program speed MLC memory
05/01/2008US20080101143 Memory device with configurable delay tracking
05/01/2008US20080101139 Memory access strobe configuration system and process
05/01/2008US20080101138 Methods of operating non-volatile memory devices to generate data strobe signals during data reading and related devices
05/01/2008US20080101137 Semiconductor memory device having a plurality of chips and capability of outputting a busy signal
05/01/2008US20080101136 Semiconductor memory device having write data through function
05/01/2008US20080101135 High-density semiconductor device
05/01/2008US20080101134 Self refresh control device
05/01/2008US20080101132 Memory output circuit and method thereof
05/01/2008US20080101131 Semiconductor memory device and method for reducing cell activation during write operations
05/01/2008US20080101130 Semiconductor device
05/01/2008US20080101129 Semiconductor memory device
05/01/2008US20080101107 Ferroelectric semiconductor memory device and method for reading the same
05/01/2008US20080101106 State storage with defined retention time
05/01/2008US20080101105 Memory Module and Method for Operating a Memory Module
04/2008
04/30/2008EP1915502A2 Memory device with a data hold latch
04/30/2008EP1497733A4 Destructive-read random access memory system buffered with destructive-read memory cache
04/30/2008DE102006051591B3 Memory chip i.e. dynamic RAM memory chip, testing method, involves determining that all data outputs of memory chips lie close to logical zero and one, if signal level at input falls below and exceeds threshold level, respectively
04/30/2008DE10120418B4 Gemeinsames Modul für einen DDR-SDRAM und einen SDRAM Common module for a DDR SDRAM and SDRAM
04/30/2008CN201054255Y Portable and onboard video/audio system
04/30/2008CN201054254Y A high sound quality accompanied digital recording and playing machine
04/30/2008CN201054084Y Electronic alarm clock capable of recording voice information
04/30/2008CN101171642A Page buffer architecture for programming, erasing and reading nanoscale resistive memory devices
04/30/2008CN101171641A Use of data latches in cache operations of non-volatile memories
04/30/2008CN101169971A Electronic hard disk
04/30/2008CN101169965A Combined read/write circuit for memory
04/30/2008CN101169964A High-density semiconductor device
04/30/2008CN101169963A Memory chip possessing high voltage bus interface
04/30/2008CN100385572C Semiconductor device and semiconductor storage device
04/30/2008CN100385570C High speed memory system, memory device, calibration method and method of synchronizing read timing
04/30/2008CN100385569C Memory sense amplifier for memory device
04/30/2008CN100385568C Memory element, method of repairing its defect memory unit automatically and method of its access
04/30/2008CN100385426C Architecture for universal serial bus-based PC flash disk
04/29/2008USRE40282 Edge transition detection circuitry for use with test mode operation of an integrated circuit memory device
04/29/2008US7366967 Methods of testing semiconductor memory devices in a variable CAS latency environment and related semiconductor test devices
04/29/2008US7366965 Semiconductor integrated circuit
04/29/2008US7366862 Method and apparatus for self-adjusting input delay in DDR-based memory systems
04/29/2008US7366827 Method and apparatus for selectively transmitting command signal and address signal
04/29/2008US7366822 Semiconductor memory device capable of reading and writing data at the same time
04/29/2008US7366821 High-speed memory system
04/29/2008US7366820 Second-cache driving/controlling circuit, second cache, RAM, and second-cache driving/controlling method
04/29/2008US7366051 Word line driver circuitry and methods for using the same
04/29/2008US7366050 Apparatus and method for data outputting
04/29/2008US7366049 Apparatus and method for updating data in a dual port memory
04/29/2008US7366047 Method and apparatus for reducing standby current in a dynamic random access memory during self refresh
04/29/2008US7366046 DRAM density enhancements
04/29/2008US7366045 Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory
04/29/2008US7366044 Systems and methods for data transfers between memory cells
04/29/2008US7366043 Current reduction circuit of semiconductor device
04/29/2008US7366042 Defective column(s) in a memory device/card is/are skipped while serial data programming is performed
04/29/2008US7366041 Input buffer for low voltage operation
04/29/2008US7366040 Method of reducing settling time in flash memories and improved flash memory