Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
07/2008
07/16/2008CN101221807A Semiconductor memory device, sense amplifier circuit and memory cell reading method
07/16/2008CN101221806A Special player
07/16/2008CN101221805A Media connecting mechanism and system using the same
07/16/2008CN101221804A Memory device and its data reading circuit
07/16/2008CN100403452C Method of measuring threshold voltage for a NAND flash memory device
07/16/2008CN100403449C Synchronized semiconductor memory
07/16/2008CN100403446C Multiport scanning chain register device and method
07/16/2008CN100403445C MRAM with midpoint generator reference
07/16/2008CN100403443C Method and apparatus for analyzing and repairing memory
07/16/2008CN100403276C Memory access method
07/15/2008US7401281 Remote BIST high speed test and redundancy calculation
07/15/2008US7400547 Semiconductor integrated circuit with power-reducing standby state
07/15/2008US7400544 Actively driven VREF for input buffer noise immunity
07/15/2008US7400543 Metal programmable self-timed memories
07/15/2008US7400542 Control selection circuit and method for a semiconductor device
07/15/2008US7400541 Circuits and methods for data bus inversion in a semiconductor memory
07/15/2008US7400540 Programmable memory and access method for the same
07/15/2008US7400539 Memory device having terminals for transferring multiple types of data
07/15/2008US7400530 Semiconductor memory
07/15/2008US7400177 Amplifier circuit having constant output swing range and stable delay time
07/10/2008WO2008082606A1 Semiconductor device and method of controlling the same
07/10/2008WO2008081426A1 Avoiding errors in a flash memory by using substitution transformations
07/10/2008WO2008039624A3 Sense amplifier circuit for low voltage applications
07/10/2008WO2008021647A3 Contactless nonvolatile memory array
07/10/2008WO2007062307A3 Method and memory system for legacy hosts
07/10/2008WO2006052992A3 High speed and low power scram macro architecture and method
07/10/2008US20080165606 Semiconductor memory device for reducing peak current during refresh operation
07/10/2008US20080165605 Method and apparatus for variable memory cell refresh
07/10/2008US20080165604 Holographic storage medium, and method and apparatus for recording/reproducing data on/from the holographic storage medium
07/10/2008US20080165603 Semiconductor memory device having sense amplifier operable as a semi-latch type and a full-latch type based on timing and data sensing method thereof
07/10/2008US20080165602 Processor Instruction Cache with Dual-Read Modes
07/10/2008US20080165601 eDRAM HIERARCHICAL DIFFERENTIAL SENSE AMP
07/10/2008US20080165598 Bi-directional resistive random access memory capable of multi-decoding and method of writing data thereto
07/10/2008US20080165597 Semiconductor memory device with debounced write control signal
07/10/2008US20080165596 Semiconductor memory device and method thereof
07/10/2008US20080165595 Maximum likelihood statistical method of operations for multi-bit semiconductor memory
07/10/2008US20080165594 Semiconductor memory device and driving method thereof
07/10/2008US20080165593 Semiconductor memory device and over driving method thereof
07/10/2008US20080165592 Semiconductor memory device, sense amplifier circuit and memory cell reading method
07/10/2008US20080165591 Semiconductor memory device and method for driving the same
07/10/2008US20080165590 Dynamic module output device and method thereof
07/10/2008US20080165589 Method and system for a serial peripheral interface
07/10/2008US20080165581 Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control
07/10/2008US20080165577 Semiconductor device
07/10/2008US20080165575 Memory cell array biasing method and a semiconductor memory device
07/10/2008US20080165573 Memory including two access devices per phase change element
07/10/2008US20080165570 Current Compliant Sensing Architecture for Multilevel Phase Change Memory
07/10/2008US20080165567 Semiconductor memory device
07/10/2008US20080165566 Non-volatile memory including sub cell array and method of writing data thereto
07/10/2008US20080165563 Semiconductor memory device
07/10/2008US20080165559 Data line layout and line driving method in semiconductor memory device
07/10/2008US20080165558 Semiconductor memory device
07/10/2008US20080164905 I/O interface circuit of intergrated circuit
07/10/2008DE112006002300T5 Verfahren und Vorrichtung zum Stapeln von DRAMS Method and device for stacking DRAMS
07/10/2008DE10338729B4 Magnetspeichervorrichtung mit größerer Referenzzelle A magnetic memory device with a larger reference cell
07/10/2008DE102007059931A1 Speichersystem, Speichersteuereinheit und Verfahren zum Betreiben einer Speichersteuereinheit Memory system, memory controller and method of operating a memory controller
07/10/2008DE102007059927A1 Verfahren zum Übertragen von Daten in einem Speichersystem und Speichersystem A method for transmitting data in a storage system and storage system
07/10/2008DE102007012902B3 Bit line pair and amplifier arrangement for use in e.g. dynamic RAM, of computer system, has read amplifiers whose positions along bit line direction are selected such that coupling paths have same coupling characteristics
07/10/2008CA2669907A1 Memory storage devices comprising different ferromagnetic material layers, and methods of making and using the same
07/09/2008CN201084429Y A music generator used in commodity packing
07/09/2008CN201084428Y An inlaid background music player
07/09/2008CN201084427Y Mobile memory
07/09/2008CN201084424Y MP3 player with improved structure
07/09/2008CN201083955Y Ipod gain device
07/09/2008CN201082102Y Telesthesia device
07/09/2008CN101218649A Apparatus and method for improving dynamic refresh in a memory device
07/09/2008CN101217057A Memory controller, memory chip and method for operating memory unit set
07/09/2008CN101217000A An infrared induction voice prompt system on urban crossings
07/09/2008CN100401421C Integrated memory having a voltage generator circuit for generating a voltage supply for a read/write amplifier
07/09/2008CN100401269C Decision feedback equalization input buffer
07/08/2008USRE40423 Multiport RAM with programmable data port configuration
07/08/2008US7398439 Semiconductor device with memory and method for memory test
07/08/2008US7398413 Memory device signaling system and method with independent timing calibration for parallel signal paths
07/08/2008US7398342 Active termination control
07/08/2008US7397727 Write burst stop function in low power DDR sDRAM
07/08/2008US7397726 Flexible RAM clock enable
07/08/2008US7397725 Single-clock, strobeless signaling system
07/08/2008US7397723 Fast read port for register file
07/08/2008US7397722 Multiple block memory with complementary data path
07/08/2008US7397719 Volatile semiconductor memory
07/08/2008US7397718 Determining relative amount of usage of data retaining device based on potential of charge storing device
07/08/2008US7397717 Serial peripheral interface memory device with an accelerated parallel mode
07/08/2008US7397716 Nonvolatile semiconductor memory device which stores multivalue data
07/08/2008US7397715 Semiconductor memory device for testing redundancy cells
07/08/2008US7397713 Flash EEprom system
07/08/2008US7397712 Pre-emphasis for strobe signals in memory device
07/08/2008US7397711 Distributed write data drivers for burst access memories
07/08/2008US7397710 Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same
07/08/2008US7397709 Method and apparatus for in-system redundant array repair on integrated circuits
07/08/2008US7397708 Technique to suppress leakage current
07/08/2008US7397695 Semiconductor memory apparatus and method for writing in the memory
07/08/2008US7397694 Magnetic memory arrays
07/08/2008US7397286 Flip-flop circuit including latch circuits
07/03/2008WO2008079958A1 Interleaved memory program and verify method, device and system
07/03/2008WO2008079661A1 Latched comparator and methods for using such
07/03/2008WO2008078866A1 Multi-level cell memory devices and methods of storing data in and reading data from the memory devices
07/03/2008WO2008078314A1 Flash memory device, system and method with randomizing for suppressing error
07/03/2008WO2008077243A1 A power up detection system for a memory device
07/03/2008WO2008077240A1 Mask programmable anti-fuse architecture
07/03/2008WO2008077239A1 A program lock circuit for a mask programmable anti-fuse memory array