Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
02/2008
02/20/2008CN101127235A Semiconductor memory device with ZQ calibration circuit
02/20/2008CN101127234A Dynamic power control of an on-die thermal sensor
02/20/2008CN100370554C Current refrence generator for magnetic RAM
02/20/2008CN100370510C Driver circuit for display device and display device
02/19/2008US7334266 Reproduction control method, program and recording medium
02/19/2008US7334174 Semiconductor integrated circuit device and error detecting method therefor
02/19/2008US7334137 Memory interface systems that couple a memory to a memory controller and are responsive to a terminal voltage that is independent of supply voltages for the memory and the memory controller
02/19/2008US7333570 Clock data recovery circuitry associated with programmable logic device circuitry
02/19/2008US7333390 Phase controlled high speed interfaces
02/19/2008US7333387 Device and method for selecting 1-row and 2-row activation
02/19/2008US7333386 Extraction of a binary code based on physical parameters of an integrated circuit through programming resistors
02/19/2008US7333382 Method and apparatus for an oscillator within a memory device
02/19/2008US7333381 Circuitry and methods for efficient FIFO memory
02/19/2008US7333380 SRAM memory device with flash clear and corresponding flash clear method
02/19/2008US7333379 Balanced sense amplifier circuits with adjustable transistor body bias
02/19/2008US7333378 Memory device that recycles a signal charge
02/19/2008US7333377 Test mode control device using nonvolatile ferroelectric memory
02/19/2008US7333376 Test mode control device using nonvolatile ferroelectric memory
02/19/2008US7333375 Repair control circuit of semiconductor memory device with reduced size
02/19/2008US7333374 Semiconductor memory device capable of replacing defective memory cell with redundant memory cell, and electronic equipment
02/19/2008US7333373 Charge pump for use in a semiconductor memory
02/19/2008US7333372 Reset circuit and integrated circuit device with reset function
02/19/2008US7333371 Non-volatile semiconductor memory device
02/19/2008US7333370 Method to prevent bit line capacitive coupling
02/19/2008US7333367 Flash memory devices including multiple dummy cell array regions
02/19/2008CA2454359C Vehicle speed display apparatus
02/14/2008WO2007120389A3 Bit line coupling
02/14/2008US20080040584 Method and Apparatus for Performing Group Floating-Point Operations
02/14/2008US20080040567 Command control circuit
02/14/2008US20080040106 Digital Recording and playback system with voice recognition capability for concurrent text generation
02/14/2008US20080037349 Ultra low-cost solid-state memory
02/14/2008US20080037348 Method for adjusting programming/erasing time in memory system
02/14/2008US20080037347 Electronic Device, Format Discrimination System and Format Discrimination Method
02/14/2008US20080037346 Memory array with a delayed wordline boost
02/14/2008US20080037345 High-speed, self-synchronized current sense amplifier
02/14/2008US20080037344 Semiconductor memory and memory system
02/14/2008US20080037343 Memory having sense time of variable duration
02/14/2008US20080037342 Apparatus and method for repairing a semiconductor memory
02/14/2008US20080037338 Self-timing circuit with programmable delay and programmable accelerator circuits
02/14/2008US20080037337 Semiconductor memory
02/14/2008US20080037336 Semiconductor memory device
02/14/2008US20080037335 Semiconductor memory device
02/14/2008US20080037334 Semiconductor device having output buffer initialization circuit and output buffer initialization method
02/14/2008US20080037333 Memory device with separate read and write gate voltage controls
02/14/2008US20080036809 Liquid ejecting apparatus
02/14/2008DE60220511T2 Verfahren und system zur optimierung der testkosten und deaktivierungsdefekte für scan- und bist-speicher Method and system for optimizing the test cost and deactivation defective for scan- and are mem
02/14/2008DE112006000661T5 Stromfühlerschaltung mit einer stromkompensierten Drainspannungsregelung The current sensing circuit with a current-compensated drain voltage regulation
02/14/2008DE102007032160A1 Verzögerungsregelkreis, Halbleiterspeicherelement und Verfahren zum Erzeugen einer Mehrzahl von verzögerten Taktsignalen Delay locked loop, semiconductor storage element and method for generating a plurality of delayed clock signals
02/14/2008DE102006036823A1 Data synchronization and buffering circuit for use in semiconductor memory e.g. dynamic RAM, buffer chip, has comparator producing release signal to connect bypass path through multiplexer when values of register random pointers are same
02/14/2008DE102006036822A1 Verfahren zum Betrieb eines Speichermoduls und Speichermodul Method for operating a memory module and memory module
02/13/2008EP1886315A1 Method to handle write mask in dram memory
02/13/2008EP1886155A2 Memory device and method having a data bypass path to allow rapid testing and calibration
02/13/2008EP1683156B1 Internal voltage reference for memory interface
02/13/2008CN201022236Y Lamp controller used by charge doll
02/13/2008CN201022015Y Voice prompt and lighting device for communication cable connection box
02/13/2008CN201022010Y Built-in finance POS voice prompter
02/13/2008CN201019018Y Shoes with music playing function
02/13/2008CN101124637A Near pad ordering logic
02/13/2008CN101124552A System and method for storaging data
02/13/2008CN101123117A Non volatile memory device and its operation method
02/13/2008CN101123111A Interface circuit
02/13/2008CN100369254C 半导体集成电路器件 The semiconductor integrated circuit device
02/13/2008CN100369156C Semiconductor storage and control method thereof
02/13/2008CN100369155C Semiconduetor storage device based on pseudo-unit method
02/13/2008CN100369154C Data induction method used for storage cell circuit
02/13/2008CN100369017C Encrypt device and method for static RAM programmable gate array chip
02/13/2008CN100368997C Encoder for correcting static data storage fault
02/12/2008US7331011 Semiconductor integrated circuit device
02/12/2008US7330953 Memory system having delayed write timing
02/12/2008US7330952 Integrated circuit memory device having delayed write timing based on read response time
02/12/2008US7330951 Apparatus and method for pipelined memory operations
02/12/2008US7330553 Audio signal reproducing apparatus
02/12/2008US7330394 Information storage device, information storage method, and information storage program
02/12/2008US7330392 Dual port semiconductor memory device
02/12/2008US7330390 Noise resistant small signal sensing circuit for a memory device
02/12/2008US7330389 Address detection system and method that compensates for process, temperature, and/or voltage fluctuations
02/12/2008US7330388 Sense amplifier circuit and method of operation
02/12/2008US7330387 Integrated semiconductor memory device
02/12/2008US7330386 Semiconductor memory device
02/12/2008US7330384 Verifying circuit and method of repairing semiconductor device
02/12/2008US7330382 Programmable DQS preamble
02/12/2008US7330381 Method and apparatus for a continuous read command in an extended memory array
02/12/2008US7330379 Semiconductor memory device having forced fail function of forcing a memory cell at a specific address to fail and method for testing same
02/12/2008US7330378 Inputting and outputting operating parameters for an integrated semiconductor memory device
02/12/2008US7330374 Nonvolatile semiconductor memory device, such as an EEPROM or a flash memory, with reference cells
02/12/2008US7330368 Three-dimensional semiconductor device provided with interchip interconnection selection means for electrically isolating interconnections other than selected interchip interconnections
02/12/2008US7330043 Semiconductor device and test method for the same
02/12/2008CA2437050C Non-destructive readout
02/07/2008WO2008015665A1 Method of avoiding errors in flash memory
02/07/2008WO2007127678A3 High-performance flash memory data transfer
02/07/2008US20080034130 Buffered Memory Having A Control Bus And Dedicated Data Lines
02/07/2008US20080031385 Clock data recovery circuitry associated with programmable logic device circuitry
02/07/2008US20080031078 High voltage generator and related flash memory device
02/07/2008US20080031069 System and method for refreshing a dram device
02/07/2008US20080031068 Dynamic memory refresh configurations and leakage control methods
02/07/2008US20080031067 Block erase for volatile memory
02/07/2008US20080031066 Method and system for independent control of voltage and its temperature co-efficient in non-volatile memory devices
02/07/2008US20080031065 Semiconductor memory device with column to be selected by bit line selection signal
02/07/2008US20080031064 Self-feedback control pipeline architecture for memory read path applications
02/07/2008US20080031063 Sense-amplifier assist (saa) with power-reduction technique