| Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197) |
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| 07/29/2008 | US7405990 Method and apparatus for in-system redundant array repair on integrated circuits |
| 07/29/2008 | US7405988 Method and apparatus for systematic and random variation and mismatch compensation for multilevel flash memory operation |
| 07/29/2008 | US7405987 Low voltage, high gain current/voltage sense amplifier with improved read access time |
| 07/29/2008 | US7405986 Redundant wordline deactivation scheme |
| 07/29/2008 | US7405985 Flexible and area efficient column redundancy for non-volatile memories |
| 07/29/2008 | US7405984 System and method for providing programmable delay read data strobe gating with voltage and temperature compensation |
| 07/29/2008 | US7405983 Diagonal matrix delay |
| 07/29/2008 | US7405981 Circuit for data bit inversion |
| 07/29/2008 | US7405980 Shared terminal memory interface |
| 07/29/2008 | US7405979 Nonvolatile memory system, semiconductor memory, and writing method |
| 07/29/2008 | US7405974 Semiconductor memory device, page buffer resource assigning method and circuit therefor, computer system and mobile electronic device |
| 07/29/2008 | US7405964 Integrated circuit to identify read disturb condition in memory cell |
| 07/29/2008 | US7405963 Dynamic data restore in thyristor-based memory device |
| 07/29/2008 | US7405623 Sensing circuit |
| 07/29/2008 | US7405362 Semiconductor devices having more than two-rows of pad structures and methods of fabricating the same |
| 07/29/2008 | US7405148 Semiconductor device having a low-resistance bus interconnect, method of manufacturing same, and display apparatus employing same |
| 07/29/2008 | CA2347765C Column redundancy circuit with reduced signal path delay |
| 07/24/2008 | WO2008089159A2 Sense amplifier with stages to reduce capacitance mismatch in current mirror load |
| 07/24/2008 | WO2008089158A2 Compensated current offset in a sensing circuit |
| 07/24/2008 | WO2008089157A2 Column leakage compensation in a sensing circuit |
| 07/24/2008 | WO2007139648A3 Method for improving the precision of a temperature-sensor circuit |
| 07/24/2008 | US20080177986 Method and software for group data operations |
| 07/24/2008 | US20080177943 Method and system for using dynamic random access memory as cache memory |
| 07/24/2008 | US20080175086 Multi-Port Dynamic Memory Structures |
| 07/24/2008 | US20080175085 Differential and Hierarchical Sensing for Memory Circuits |
| 07/24/2008 | US20080175084 Semiconductor memory device and sense amplifier circuit |
| 07/24/2008 | US20080175083 Memory cell access circuit |
| 07/24/2008 | US20080175082 Serial power capacitor device |
| 07/24/2008 | US20080175081 Semiconductor memory device and operation control method thereof |
| 07/24/2008 | US20080175080 Semiconductor memory device and test method thereof |
| 07/24/2008 | US20080175079 Test scheme for fuse circuit |
| 07/24/2008 | US20080175078 Method and apparatus for synchronizing data from memory arrays |
| 07/24/2008 | US20080175077 Novel write VCCMIN improvement scheme |
| 07/24/2008 | US20080175076 Semiconductor memory device |
| 07/24/2008 | US20080175075 Sense amplifier for non-volatile memories |
| 07/24/2008 | US20080175074 Switched capacitor charge sharing technique for integrated circuit devices enabling signal generation of disparate selected signal values |
| 07/24/2008 | US20080175073 Sense amplifiers and semiconductor memory devices for reducing power consumption and methods for operating the same |
| 07/24/2008 | US20080175072 Fast data access through page manipulation |
| 07/24/2008 | US20080175071 Methods of Operating Memory Systems Including Memory Devices Set to Different Operating Modes |
| 07/24/2008 | US20080175070 Early Read After Write Operation Memory Device, System And Method |
| 07/24/2008 | US20080175067 Semiconductor memory device |
| 07/24/2008 | US20080175065 Method and apparatus for storing page data |
| 07/24/2008 | US20080175054 Methods and systems for memory devices |
| 07/24/2008 | US20080175051 Semiconductor memory |
| 07/24/2008 | US20080175043 Method and apparatus for initializing reference cells of a toggle switched mram device |
| 07/24/2008 | US20080175041 Magnetic memory device, method for writing into magnetic memory device and method for reading magnetic memory device |
| 07/24/2008 | US20080175040 Semiconductor memory device |
| 07/24/2008 | US20080175035 Non-volatile resistance changing for advanced memory applications |
| 07/24/2008 | US20080174336 Circuit and method for detecting skew of transistor in semiconductor device |
| 07/24/2008 | DE102007060782A1 Kompensierung für Data Strobe-Zeitgebung Compensation for data strobe timing |
| 07/24/2008 | DE102004016403B4 Nichtflüchtiger Halbleiterspeicherbaustein sowie zugehörige Betriebs- und Leseverfahren A non-volatile semiconductor memory device and associated operating and reading method |
| 07/23/2008 | EP1947651A2 Semiconductor memory |
| 07/23/2008 | EP1946545A1 Apparatus, method and computer program product providing synchronization of memory card operation during dvb-h reception |
| 07/23/2008 | EP1946322A1 Determining optimal time instances to sense the output of a memory array |
| 07/23/2008 | EP1946214A2 Clock signal generation techniques for memories that do not generate a strobe |
| 07/23/2008 | CN101227758A Method for eliminating noise of audio equipment and audio equipment with silencing apparatus using the method |
| 07/23/2008 | CN101226767A Read-write control circuit, method and apparatus for two-port RAM |
| 07/23/2008 | CN101226766A Audio play device automatically adjusting play parameter |
| 07/23/2008 | CN101226765A Multi-chip packaged flash memory device and reading method of status data thereof |
| 07/23/2008 | CN101226764A Calibration circuit, semiconductor device with the same, and output characteristic adjusting method of semiconductor device |
| 07/23/2008 | CN101226456A Method and system for a serial peripheral interface |
| 07/23/2008 | CN100405499C Memory modular and memory system |
| 07/23/2008 | CN100405327C Memory system,memory device and output data strobe signal generating method |
| 07/23/2008 | CN100405247C Teminal, data processing device and method, and transmission method for data processing device |
| 07/22/2008 | US7404116 Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRAM at internally doubled clock testing application |
| 07/22/2008 | US7404018 Read latency control circuit |
| 07/22/2008 | US7403447 Method for stabilizing electronic circuit operation and electronic apparatus using the same |
| 07/22/2008 | US7403446 Single late-write for standard synchronous SRAMs |
| 07/22/2008 | US7403444 Selectable memory word line deactivation |
| 07/22/2008 | US7403440 Electronic memory apparatus and method for operating an electronic memory apparatus |
| 07/22/2008 | US7403439 Bitline leakage limiting with improved voltage regulation |
| 07/22/2008 | US7403438 Memory array architecture and method for high-speed distribution measurements |
| 07/22/2008 | US7403437 ROM test method and ROM test circuit |
| 07/22/2008 | US7403436 Non-volatile semiconductor memory device |
| 07/22/2008 | US7403434 System for controlling voltage in non-volatile memory systems |
| 07/22/2008 | US7403433 Self timing write architecture for semiconductor memory and method for providing the same |
| 07/22/2008 | US7403432 Differential read-out circuit for fuse memory cells |
| 07/22/2008 | US7403431 Method of reading a flash memory device |
| 07/22/2008 | US7403423 Sensing scheme for low-voltage flash memory |
| 07/22/2008 | US7403417 Non-volatile semiconductor memory device and method for operating a non-volatile memory device |
| 07/17/2008 | WO2008085701A2 Method and apparatus for variable memory cell refresh |
| 07/17/2008 | WO2008011441A3 Method for configuring compensation for coupling between adjacent storage elements in a nonvolatile memory |
| 07/17/2008 | WO2008005057A3 Partitioned random access and read only memory |
| 07/17/2008 | WO2007136812A3 Memory array having row redundancy and method |
| 07/17/2008 | WO2007134062A3 Sensing light and sensing the state of a memory cell |
| 07/17/2008 | US20080170456 Memory refresh method and system |
| 07/17/2008 | US20080170455 Compensated current offset in a sensing circuit |
| 07/17/2008 | US20080170454 Sense amplifier with stages to reduce capacitance mismatch in current mirror load |
| 07/17/2008 | US20080170453 Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory |
| 07/17/2008 | US20080170452 Data output circuit in semiconductor memory device |
| 07/17/2008 | US20080170447 Storing Information in a Memory |
| 07/17/2008 | US20080170442 Column leakage compensation in a sensing circuit |
| 07/17/2008 | US20080170437 Semiconductor memory device having a plurality of chips and capability of outputting a busy signal |
| 07/17/2008 | US20080170433 Word line drivers in non-volatile memory device and method having a shared power bank and processor-based systems using same |
| 07/17/2008 | US20080170432 Magnetic random access memory and write method of the same |
| 07/17/2008 | US20080170431 Driving method and system for a phase change memory |
| 07/17/2008 | DE10058227B4 Halbleiterspeicherbauelement, Durchlass-/Zwischenspeichereinheit hierfür und zugehöriges Datenübertragungsverfahren A semiconductor memory device, transmission / latch unit therefor, and associated data transfer process |
| 07/16/2008 | EP1943664A2 A method, system and computer-readable code for testing of flash memory |
| 07/16/2008 | CN201087871Y Automatic reminding device for medical use |
| 07/16/2008 | CN101223500A Auto purge of serial use devices |