Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002)
11/1991
11/19/1991US5067104 Programmable protocol engine having context free and context dependent processes
11/19/1991US5067075 Method of direct memory access control
11/19/1991US5067071 Multiprocessor computer system employing a plurality of tightly coupled processors with interrupt vector bus
11/19/1991CA1292325C Data processing system having a bus command generated by one subsystem on behalf of another subsystem
11/19/1991CA1292324C Multitask subscription data retrieval system
11/14/1991WO1991017633A1 Addressing device
11/13/1991EP0456447A2 Data processing apparatus utilizing CPU
11/13/1991EP0456410A2 Adapter card
11/13/1991EP0456395A2 System and method for monitoring electronic data processing equipment
11/13/1991EP0456378A2 An arrangement for automated troubleshooting using selective advice and a learning knowledge base
11/13/1991EP0456249A2 System for integrating application programs in a heterogeneous network enviroment
11/12/1991US5065356 Shared use of keyboard and memory lines
11/12/1991US5065314 Method and circuit for automatically communicating in two modes through a backplane
11/12/1991US5065313 Digital computer system having circuit for regulation of I/O command recovery time
11/12/1991US5065154 Digitally addressble electronic device with interchanged and inverted address lines
11/12/1991US5065141 Expanded register rack for a programmable logic controller
11/12/1991US5065052 Arbiter circuit using plural-reset rs flip-flops
11/06/1991EP0455442A2 Fault detection in link-connected systems
11/06/1991EP0455402A2 Automatic discovery of network elements
11/06/1991EP0454992A2 Suppression of electrical interferences from an electronic circuit
11/05/1991US5063498 Data processing device with direct memory access function processed as an micro-code vectored interrupt
11/05/1991US5063494 Programmable data communications controller
11/05/1991US5063362 Suppression of electrical interferences from an electronic circuit
10/1991
10/31/1991WO1991016680A1 Integrated circuit i/o using a high preformance bus interface
10/30/1991EP0454609A2 VLSI chip circuit having a reduced current transient
10/30/1991EP0454608A2 Method for automated process delay within a data processing system
10/30/1991EP0454605A2 Bus request device in a direct memory access (DMA) system
10/30/1991EP0454303A2 Electronic data format conversion system and method
10/30/1991EP0454096A2 Interrupt control circuit and microcomputer system comprising the same
10/30/1991EP0454064A2 Data transmission system
10/30/1991EP0453863A2 Methods and apparatus for implementing a media access control/host system interface
10/29/1991US5062076 Cascadable, high-bandwidth, multi-channel image transfer controller
10/29/1991US5062073 Input output control system using a fifo to record access information of control registers by a master device
10/29/1991US5062059 Apparatus and method for communication between host CPU and remote terminal
10/29/1991US5062047 Translation method and apparatus using optical character reader
10/29/1991US5062044 Temporary bus master for use in a digital system having asynchronously communicating sub-systems
10/29/1991US5062043 Information collecting and distributing system providing plural sources and destinations with synchronous alternating access to common storage
10/29/1991US5062042 System for managing data which is accessible by file address or disk address via a disk track map
10/29/1991US5062035 Time slot allocation for loop networks
10/29/1991US5061824 Backpanel having multiple logic family signal layers
10/29/1991CA1291576C Concurrent multi-protocol i/o controller
10/29/1991CA1291575C Level converting bus extender with subsystem selection signal decoding enabling connection to microprocessor
10/24/1991WO1991016679A1 Multichannel backplane bus system architecture
10/24/1991DE4012544A1 Identical subscriber address recognition in data transmission system - generating random numbers by slave stations in acknowledgement of master station test transmission
10/24/1991CA2079671A1 Multichannel backplane bus system architecture
10/23/1991EP0453199A2 Computer system with synchronous bus
10/23/1991EP0453171A2 Method for substantially eliminating hold time violations in implementing high speed logic circuits or the like
10/23/1991EP0453153A2 Order independent rule-based program specification system
10/22/1991US5060186 High-capacity memory having extended addressing capacity in a multiprocessing system
10/22/1991US5060149 Method for controlling multiple terminals from a single logically partitioned input device
10/22/1991US5060145 Memory access system for pipelined data paths to and from storage
10/22/1991US5060142 System which matches a received sequence of channel commands to sequence defining rules for predictively optimizing peripheral subsystem operations
10/22/1991US5060141 Multiprocessor system having unidirectional communication paths
10/22/1991US5060140 Universal programmable data communication connection system
10/22/1991US5060139 Futurebus interrupt subsystem apparatus
10/22/1991US5060138 Apparatus for use with a computing device for generating a substitute acknowledgement to an input when the computing device is in an operational hiatus
10/22/1991US5060134 Action direction port expansion circuit and system
10/22/1991US5060111 Radial type of parallel system bus structure
10/22/1991US5059830 Integrated circuit using bus driver having reduced area
10/22/1991CA1291270C Method and apparatus for specification of communication parameters
10/18/1991CA2035952A1 Order independent rule-based program specification system
10/17/1991WO1991015825A1 Method and apparatus for an enhanced computer system interface
10/17/1991WO1991015824A1 Controlled bus reselection interface and method
10/16/1991EP0451523A2 Interface for connecting a computer to a digital telecommunications terminal
10/16/1991EP0451516A1 Improved SCSI device in a small computer system
10/16/1991EP0451426A1 Multiple-access control for a communication system with order pad passing
10/16/1991EP0441798A4 Entity management system
10/15/1991US5058143 Digital communications systems
10/15/1991US5058110 Protocol processor
10/15/1991US5058064 Memory device having address control function
10/15/1991US5058057 Link control system communicating between terminals
10/15/1991US5058056 Workstation takeover control
10/15/1991US5058054 Data transmission device for interfacing between a first rate data acquisition system and a second rate data processing system
10/15/1991US5058053 High performance computer system with unidirectional information flow
10/15/1991US5058051 Address register processor system
10/15/1991US5058005 Computer system with high speed data transfer capabilities
10/15/1991US5057998 Data transfer control unit
10/15/1991US5057997 Interruption systems for externally changing a context of program execution of a programmed processor
10/15/1991US5057935 Method for confirmation of document recipient in a data processing system
10/15/1991US5057829 Computer networking apparatus
10/14/1991WO1991016678A1 Method of resetting adapter module at failing time and computer system executing said method
10/09/1991EP0450871A2 Interfaces for transmission lines
10/09/1991EP0450811A2 Integrated circuit
10/09/1991EP0450233A2 Bus access for digital computer system
10/09/1991EP0449985A1 Apparatus and method for using encoded video recorder/player timer preprogramming information
10/09/1991CN1055252A Bus monitor with selective capture of independently occurring events from multiple sources
10/08/1991US5056110 Differential bus with specified default value
10/08/1991US5056060 Printed circuit card with self-configuring memory system for non-contentious allocation of reserved memory space among expansion cards
10/08/1991US5056058 Communication protocol for predicting communication frame type in high-speed processing system
10/08/1991US5056011 Direct memory access controller with expedited error control
10/08/1991US5056010 Pointer based DMA controller
10/08/1991US5056005 Data buffer device using first-in first-out memory and data buffer array device
10/08/1991CA1290406C Finite metastable time synchronizer
10/03/1991WO1991014989A1 A repeater/switch for distributed arbitration digital data buses
10/02/1991EP0449579A2 A logic simulation machine
10/02/1991EP0449458A1 Network-field interface for manufacturing systems
10/02/1991EP0449408A2 System adaptable for managing data
10/02/1991EP0448958A2 Semiconductor integrated circuit having non-volatile memory cells for controlling a predetermined function
10/02/1991EP0448881A2 Interference suppression system
10/02/1991DE4009685A1 Initialising procedure for single Bus multiprocessor system - uses arbitrator unit to allocate user identification numbers and to determine mutually acceptable data handling parameters
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