| Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002) |
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| 05/02/1996 | CA2203391A1 A method for internal communication in a telecommunications system |
| 05/01/1996 | EP0710046A2 ATM cell Scheduler |
| 05/01/1996 | EP0709994A2 Communications management between client and server processes |
| 05/01/1996 | EP0709993A2 Phase demodulation method by measuring the time between zero-crossings |
| 05/01/1996 | EP0709987A2 Bypass switching and messaging mechanism for providing intermix data transfer for a fiber optic switch |
| 05/01/1996 | EP0709986A2 Channel module for a fiber optic switch with a bit sliced memory architecture for data frame storage |
| 05/01/1996 | EP0709803A2 Contactless IC card system and communication method thereof |
| 05/01/1996 | EP0709787A1 Data processing system comprising at least two processors |
| 05/01/1996 | EP0709786A1 Semiconductor memory with a timing controlled for receiving data at a semiconductor memory module to be accessed |
| 05/01/1996 | EP0709785A2 Internal state determining apparatus |
| 05/01/1996 | EP0709784A2 Bus locking mechanism in a computer system |
| 05/01/1996 | EP0709780A1 Method and apparatus for remote retry in a data processing system |
| 05/01/1996 | EP0709779A2 Virtual shared disks with application-transparent recovery |
| 05/01/1996 | EP0709763A2 Network hibernation system |
| 05/01/1996 | EP0591345B1 Method and system for monitoring a computer system |
| 05/01/1996 | CN1121758A Multimedia communications network |
| 05/01/1996 | CN1121604A Communication circuit |
| 05/01/1996 | CA2154716A1 Bypass switching and messaging mechanism for providing intermix data transfer for a fiber optic switch |
| 04/30/1996 | US5513377 Input-output element has self timed interface using a received clock signal to individually phase aligned bits received from a parallel bus |
| 04/30/1996 | US5513374 On-chip interface and DMA controller with interrupt functions for digital signal processor |
| 04/30/1996 | US5513372 Peripheral interface having hold control logic for generating stall signals to arbitrate two read and one write operations between processor and peripheral |
| 04/30/1996 | US5513368 Computer I/O adapters for programmably varying states of peripheral devices without interfering with central processor operations |
| 04/30/1996 | US5513367 Multiprocessor system having respective bus interfaces that transfer data at the same time |
| 04/30/1996 | US5513364 Data transfer device and multiprocessor system |
| 04/30/1996 | US5513347 Data transfer system |
| 04/30/1996 | US5513343 Network management system |
| 04/30/1996 | US5513334 Memory device with switching of data stream modes |
| 04/30/1996 | US5513332 Database management coprocessor for on-the-fly providing data from disk media to all without first storing data in memory therebetween |
| 04/30/1996 | US5513329 For expanding the functionality of the computer system |
| 04/30/1996 | US5513327 Integrated circuit I/O using a high performance bus interface |
| 04/30/1996 | US5513325 Technique for coupling CTOS units to non-CTOS host |
| 04/30/1996 | US5513324 Method and apparatus using network variables in a multi-node network |
| 04/30/1996 | US5513323 Method and apparatus for multistage document format transformation in a data processing system |
| 04/30/1996 | US5513321 Multiprocessor system discharging data in networking apparatus in response to off-line information from receiver-side processor |
| 04/30/1996 | US5513320 Transmit data descriptor structure in a media access control/host system interface that implements flexible transmit data descriptor structure unit |
| 04/30/1996 | US5513126 Network having selectively accessible recipient prioritized communication channel profiles |
| 04/30/1996 | US5512888 Communications system having a semiconductor integrated circuit for simultaneous mode control and a system control method |
| 04/30/1996 | US5512851 For processing data |
| 04/30/1996 | CA2030888C Cache data consistency mechanism for workstations and servers with an i/o cache |
| 04/28/1996 | CA2153918A1 Switch element for fibre channel networks |
| 04/28/1996 | CA2153823A1 Channel module for a fiber optic switch with bit sliced memory architecture for data frame storage |
| 04/25/1996 | WO1996012270A1 Time compression/expansion without pitch change |
| 04/25/1996 | WO1996012261A1 System for distributing and selecting audio and video information and method implemented by said system |
| 04/25/1996 | WO1996012260A1 Audiovisual distribution system |
| 04/25/1996 | WO1996012259A1 Home digital audiovisual information recording and playback apparatus |
| 04/25/1996 | WO1996012258A1 Intelligent digital audiovisual playback system |
| 04/25/1996 | WO1996012255A1 Intelligent digital audiovisual playback system |
| 04/25/1996 | WO1996012250A1 Improvement in communication between data processing apparatus and peripheral device thereof |
| 04/25/1996 | WO1996012249A1 Improvement in data collection of data processing apparatus from peripherals thereof |
| 04/25/1996 | WO1996012230A1 System and method for processing of memory data and communication system comprising such system |
| 04/25/1996 | WO1996005703A3 Method for transfer of data files from a mass storage device to a post-processing system |
| 04/25/1996 | DE3490263C2 Control channel interface circuit |
| 04/25/1996 | CA2202863A1 System and method for processing of memory data and communication system comprising such system |
| 04/25/1996 | CA2201915A1 Intelligent digital audiovisual playback system |
| 04/24/1996 | EP0708405A1 Multiplexer and integrated processor incorporating same |
| 04/24/1996 | EP0707726A1 Memory control device for an assay apparatus |
| 04/24/1996 | EP0595828B1 Communication apparatus and method for transferring image data from a source to one or more receivers |
| 04/24/1996 | EP0471806B1 Method of personalising an electronic module, electronic circuit and module which are designed for the implementation of this method |
| 04/24/1996 | EP0436559B1 Data processing network |
| 04/24/1996 | CN1121282A Parameter setting method for PLC communication system |
| 04/24/1996 | CN1121216A System and method for efficient caching in a distributed file system |
| 04/24/1996 | CN1121209A EEPROM altering frequency raising method through indexing |
| 04/24/1996 | CN1121206A Input buffer device for a printer using an fifo and data input method |
| 04/23/1996 | US5511229 Data processing system having a switching network connecting multiple peripheral devices using data paths capable of different data bus widths |
| 04/23/1996 | US5511221 Parallel processor system for detecting the end of data transmission |
| 04/23/1996 | US5511219 Mechanism for implementing vector address pointer registers in system having parallel, on-chip DSP module and CPU core |
| 04/23/1996 | US5511214 On-line processing system and overload suppressing method |
| 04/23/1996 | US5511208 Locating resources in computer networks having cache server nodes |
| 04/23/1996 | US5511188 Networked facilities management system with time stamp comparison for data base updates |
| 04/23/1996 | US5511182 Programmable pin configuration logic circuit for providing a chip select signal and related method |
| 04/23/1996 | US5511171 Apparatus for live bus insertion of add-on devices |
| 04/23/1996 | US5511170 Digital bus data retention |
| 04/23/1996 | US5511169 Data transmission apparatus and a communication path management method therefor |
| 04/23/1996 | US5511166 Method and apparatus for receive frame sorting in a media access control/host system interface unit |
| 04/23/1996 | US5511165 Method and apparatus for communicating data across a bus bridge upon request |
| 04/23/1996 | US5511152 Memory subsystem for bitmap printer data controller |
| 04/23/1996 | US5511024 Dynamic random access memory system |
| 04/23/1996 | US5510732 Synchronizer circuit and method for reducing the occurrence of metastability conditions in digital systems |
| 04/23/1996 | US5510701 Inactive state termination tester |
| 04/18/1996 | WO1996011440A1 Shared memory system |
| 04/18/1996 | WO1996011436A1 Delivery of data including preloaded advertising data |
| 04/18/1996 | WO1996011430A2 Coherency and synchronization mechanism for i/o channel controllers in a data processing system |
| 04/18/1996 | WO1996010904A2 Digital signal processor |
| 04/17/1996 | EP0707271A1 Computer system speed control |
| 04/17/1996 | EP0707268A2 Easily programmable memory controller which can access different speed memory devices on different cycles |
| 04/17/1996 | EP0707266A1 Methods and apparatus for a data transfer mechanism in the field of computer systems |
| 04/17/1996 | EP0706687A1 High-speed cpu interconnect bus architecture |
| 04/17/1996 | EP0649542A4 Method and apparatus for a unified parallel processing architecture. |
| 04/17/1996 | CN1120700A Automation method for composing official document |
| 04/17/1996 | CN1120698A Virtual line-up device |
| 04/17/1996 | CN1031607C Personal computer with riser connector for alternate master |
| 04/16/1996 | US5509139 Circuit for disabling an address masking control signal using OR gate when a microprocessor is in a system management mode |
| 04/16/1996 | US5509138 Method for determining speeds of memory modules |
| 04/16/1996 | US5509136 Data processing system including different throughput access sources accessing main storage in same direction |
| 04/16/1996 | US5509127 In a central processing module |
| 04/16/1996 | US5509125 System and method for fair arbitration on a multi-domain multiprocessor bus |
| 04/16/1996 | US5509124 Coupled synchronous-asychronous bus structure for transferring data between a plurality of peripheral input/output controllers and a main data store |
| 04/16/1996 | US5509123 Distributed autonomous object architectures for network layer routing |
| 04/16/1996 | US5509122 Configurable, recoverable parallel bus |
| 04/16/1996 | US5509121 Multi-protocol communication control apparatus |