Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002)
12/1995
12/05/1995US5473499 Hot pluggable motherboard bus connection method
12/05/1995US5473264 Methods and apparatus for electrically terminating a high speed communications pathway
12/05/1995US5473143 ATM/POS based electronic mail system
12/05/1995CA2046950C Expert system method for performing window protocol-based data flow analysis within a data communication network
12/01/1995CA2124771A1 Switching module for redundant local area network
11/1995
11/30/1995WO1995032573A1 File transfer mechanism
11/30/1995WO1995032549A1 Method and apparatus for distributing clock signals with minimal skew
11/30/1995WO1995032505A1 Memory device
11/30/1995WO1995032475A1 Method and apparatus for maintaining transaction ordering and arbitrating in a bus bridge
11/30/1995WO1995032474A1 Method and apparatus for maintaining transaction ordering and supporting deferred replies in a bus bridge
11/30/1995WO1995032463A1 A system for generating globally unique object indentities
11/30/1995CA2191113A1 Memory device
11/29/1995EP0684720A2 System and method for transmitting sequence dependent messages in a required sequence
11/29/1995EP0684563A1 Flexible bus routing structure
11/29/1995EP0684560A1 Automatic addressing of information bus devices
11/29/1995EP0684556A1 Information processing system
11/29/1995EP0684545A1 Printer controller
11/29/1995EP0684544A1 System and method for merging data from two registers
11/29/1995EP0684533A1 Processor master/slave for the management of a communication protocol
11/29/1995EP0683951A1 Multimedia distribution system
11/29/1995EP0683910A1 Communication bus system and station for use in such system
11/29/1995EP0683907A1 Method for providing mutual authentication of a user and a server on a network
11/28/1995US5471672 Method for implementing a high speed computer graphics bus
11/28/1995US5471640 Programmable disk array controller having n counters for n disk drives for stripping data where each counter addresses specific memory location by a count n
11/28/1995US5471639 In an electronic data processing system
11/28/1995US5471638 Bus interface state machines with independent access to memory, processor and registers for concurrent processing of different types of requests
11/28/1995US5471637 Method and apparatus for conducting bus transactions between two clock independent bus agents of a computer system using a transaction by transaction deterministic request/response protocol and burst transfer
11/28/1995US5471632 System for transferring data between a processor and a system bus including a device which packs, unpacks, or buffers data blocks being transferred
11/28/1995US5471620 Data processor with means for separately receiving and processing different types of interrupts
11/28/1995US5471618 System for classifying input/output events for processes servicing the events
11/28/1995US5471617 Computer management system and associated management information base
11/28/1995US5471609 Method for identifying a system holding a `Reserve`
11/28/1995US5471607 Multi-phase multi-access pipeline memory system
11/28/1995US5471601 Memory device and method for avoiding live lock of a DRAM with cache
11/28/1995US5471590 Bus master arbitration circuitry having improved prioritization
11/28/1995US5471588 Technique and circuit for providing two or more processors with time multiplexed access to a shared system resource
11/28/1995US5471587 For enabling internal data processing logic
11/28/1995US5471586 Interface system having plurality of channels and associated independent controllers for transferring data between shared buffer and peripheral devices independently
11/28/1995US5471585 Personal computer system with input/output controller having serial/parallel ports and a feedback line indicating readiness of the ports
11/28/1995US5471583 FIFO buffer having write counter for generating empty flag value to be compared with read pointer value to indicate the buffer is full
11/28/1995US5471581 Elastic configurable buffer for buffering asynchronous data
11/28/1995US5471521 Distributed system for call processing
11/28/1995US5471488 Clock fault detection circuit
11/28/1995US5471470 Computer-based multifunction personal communications system
11/28/1995US5471399 Network management system and network status display method
11/28/1995US5471318 Multimedia communications network
11/26/1995CA2149824A1 Flexible bus routing structure
11/26/1995CA2149823A1 Automatic addressing of information bus devices
11/23/1995WO1995031777A1 Method and apparatus for configuring multiple agents in a computer system
11/23/1995WO1995027242A3 Methods for monitoring a plurality of remote local units connected in a network and generating messages therefrom, and a device employed in said local units
11/23/1995DE4417977A1 Arrangement for signalling between processing units
11/23/1995DE4417316A1 Inter-microprocessor data transfer system
11/23/1995DE19507330A1 Detector for input=output states of first-in-first-out memory
11/22/1995EP0683492A2 Storage reading apparatus
11/22/1995EP0683470A2 IC card-type radio communication device
11/22/1995EP0683461A1 Integrated processor employing improved address decoding method
11/22/1995EP0683460A1 Method and apparatus for address decoding within an integrated processor
11/22/1995EP0683459A1 Coherent transaction ordering in multi-tiered bus system
11/22/1995EP0683448A1 Method and apparatus for synchronous data transmission between digital devices operating at frequencies having a P/Q integer ratio
11/22/1995EP0682833A1 Flow control by evaluating network load.
11/22/1995EP0682792A1 Method for communicating with a portable data medium
11/22/1995EP0682791A1 Network adapter with host interrupt and indication management
11/22/1995CN1112261A Speech information processor
11/22/1995CN1112260A Arbitrator device capable of readily modifying the structure
11/21/1995US5469577 Providing alternate bus master with multiple cycles of bursting access to local bus in a dual bus system including a processor local bus and a device communications bus
11/21/1995US5469571 Operating system architecture using multiple priority light weight kernel task based interrupt handling
11/21/1995US5469565 Personal computer for disabling resume mode upon replacement of HDD
11/21/1995US5469561 Apparatus and method for controlling the running of a data processing apparatus
11/21/1995US5469558 Dynamically reconfigurable memory system with programmable controller and FIFO buffered data channels
11/21/1995US5469554 Detecting the presence of a device on a computer system bus by altering the bus termination
11/21/1995US5469548 Disk array controller having internal protocol for sending address/transfer count information during first/second load cycles and transferring data after receiving an acknowldgement
11/21/1995US5469547 Asynchronous bus interface for generating individual handshake signal for each data transfer based on associated propagation delay within a transaction
11/21/1995US5469546 Method for retrying recording information into a next logical block by sending sense data including address information to host computer and responding to command therefrom
11/21/1995US5469545 Expandable communication system with data flow control
11/21/1995US5469544 Central processing unit address pipelining
11/21/1995US5469437 Network chip with auto sensing and reconfiguration
11/21/1995US5469436 Polling-type digital communications system having pseudo-balanced mode
11/21/1995US5469435 Bus deadlock avoidance during master split-transactions
11/21/1995CA2055071C Serial network topology generator
11/16/1995WO1995030960A2 Providing a master device with slave device capability information
11/16/1995WO1995030946A1 System for synchronous transmissions between digital devices
11/16/1995DE4416795A1 Redundant-configurable data transfer system for programmable controller in industrial process
11/16/1995DE4232590C2 Einrichtung zum Betrieb eines Mikrocomputersystems Means for operating a microcomputer system
11/16/1995CA2188121A1 Providing a master device with slave device capability information
11/15/1995EP0682429A2 A method and apparatus for executing a distributed algorithm or service on a simple network management protocol based computer network
11/15/1995EP0682316A1 Interactive multimedia system
11/15/1995EP0682313A1 System and procedure for detection of a fault in a chained series of control blocks
11/15/1995EP0682310A1 Method and system for microcode loading in a node of a distributed data processing system
11/15/1995EP0682307A1 Method and apparatus for enabling pipelining of buffered data
11/15/1995EP0681719A1 Method of operating character mode programs on block mode terminals.
11/15/1995EP0681718A1 System for dividing processing tasks into signal processor and decision-making microprocessor interfacing
11/15/1995CN1111775A Audio conferencing system
11/15/1995CN1111774A Dynamic management of snoop granularity for a coherent asynchronour DMA cache
11/14/1995US5467465 Two clock method for synchronizing a plurality of identical processors connected in parallel
11/14/1995US5467456 High speed bus branches with compact physical spacing
11/14/1995US5467455 Data processing system and method for performing dynamic bus termination
11/14/1995US5467454 Bus use request adjusting apparatus allowing changing priority levels
11/14/1995US5467453 Circuit for providing automatic SCSI bus termination
11/14/1995US5467435 System and method for mode switching
11/14/1995US5467369 AUI to twisted pair loopback
1 ... 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 ... 1581