Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002)
11/1995
11/14/1995US5467359 Apparatus for generating and checking the error correction codes of messages in a message switching system
11/14/1995US5467352 Method and apparatus for improved throughput in a multi-node communication system with a shared resource
11/14/1995US5467351 Extendible round robin local area hub network
11/14/1995US5467295 In a computer system
11/14/1995CA2148153A1 Interactive multimedia system
11/11/1995CA2145921A1 Method and apparatus for executing a distributed algorithm or service on a simple network management protocol based computer network
11/09/1995WO1995030191A1 Apparatus and method for network access through modular connections
11/09/1995WO1995030190A1 Transmitting between hand-held and desktop computers
11/09/1995WO1995030184A1 Pcmcia interface card for input devices such as barcode scanning engines
11/09/1995DE4415398A1 Interface test device e.g. for X=ray diagnostic unit
11/09/1995CA2362110A1 Pcmcia interface card for input devices such as barcode scanning engines
11/08/1995EP0681297A2 Cartridge programming system for game programs
11/08/1995EP0681237A1 Method and apparatus for preemptable multiplexing of connections to input/output devices
11/08/1995EP0680644A1 Multi-functionality user-interface downwards compatible with single-functionality application software
11/08/1995EP0680636A1 Interface apparatus
11/08/1995EP0559736B1 Medicament dispensing device
11/08/1995EP0482167B1 Addressing device
11/07/1995US5465364 Method and system for providing device driver support which is independent of changeable characteristics of devices and operating systems
11/07/1995US5465355 Establishing and restoring paths in a data processing I/O system
11/07/1995US5465345 Parallel processing of received and transmitted bit stream in telecommunications equipment including a DSP and supporting HDLC/SDLC protocols
11/07/1995US5465343 Shared memory array for data block and control program storage in disk drive
11/07/1995US5465340 Direct memory access controller handling exceptions during transferring multiple bytes in parallel
11/07/1995US5465338 Disk drive system interface architecture employing state machines
11/07/1995US5465333 Data transfer apparatus
11/07/1995US5465332 Selectable 8/16 bit DMA channels for "ISA" bus
11/07/1995US5465331 Apparatus having three separated and decentralized processors for concurrently and independently processing packets in a communication network
11/07/1995US5465167 Using an image from a form in automatic creation of a form or sheet
11/07/1995US5465106 Generic driver interface card
11/07/1995US5465042 Method for determining the number of terminators connected to a bus
11/02/1995WO1995029564A1 Service creation apparatus for a communications network
11/02/1995WO1995029548A1 Data transmission network
11/02/1995WO1995029450A1 Data storage
11/02/1995EP0680185A2 A distributed computer system
11/02/1995EP0680152A2 Dynamic compression-rate selection arrangement
11/02/1995EP0680010A2 Communications link module
11/02/1995EP0679998A1 Intelligent memory-based input/output system
11/02/1995EP0679997A1 Data processing system having a function of data transfer between microprocessor and memory in burst mode
11/02/1995EP0679982A1 System and method for controlling a peripheral bus clock signal
11/02/1995EP0679307A1 Delay line separator for data bus
11/02/1995EP0679275A1 A communication node with a first bus configuration for arbitration and a second bus configuration for data transfer
11/02/1995EP0471681B1 Real-time adjustable-transform device driver for physical devices
10/1995
10/31/1995US5463762 I/O subsystem with header and error detection code generation and checking
10/31/1995US5463756 Memory control unit and associated method for changing the number of wait states using both fixed and variable delay times based upon memory characteristics
10/31/1995US5463755 High-performance, multi-bank global memory card for multiprocessor systems
10/31/1995US5463753 Method and apparatus for reducing non-snoop window of a cache controller by delaying host bus grant signal to the cache controller
10/31/1995US5463752 Data processing system
10/31/1995US5463743 Method of improving SCSI operations by actively patching SCSI processor instructions
10/31/1995US5463740 Data control device generating different types of bus requests and transmitting requests directly to one of a number of arbiters for obtaining access to a respective bus
10/31/1995US5463739 Apparatus for vetoing reallocation requests during a data transfer based on data bus latency and the number of received reallocation requests below a threshold
10/31/1995US5463736 Data processing system
10/31/1995US5463735 Method of downloading information stored in an arching device to destination network controller through intermediate network controllers in accordance with routing information
10/31/1995US5463733 Failure recovery apparatus and method for distributed processing shared resource control
10/31/1995US5463658 Low impact collision detection method
10/31/1995US5463646 Method for error correction of a transmitted data word
10/31/1995US5463331 Programmable slew rate CMOS buffer and transmission line driver with temperature compensation
10/26/1995WO1995028777A1 Wireless optical communication system with adaptive data rates and/or adaptive levels of optical power
10/26/1995WO1995028677A1 Efficient addressing of large memories
10/26/1995WO1995028673A1 Trainable user interface translator
10/26/1995DE4429433C1 Address association method for modular stored program controller
10/26/1995DE19508940A1 Verfahren zum Betrieb eines Agenten A method of operating an agent
10/26/1995CA2188139A1 Trainable user interface translator
10/25/1995EP0678990A2 Zero latency synchronizer method and apparatus for system having at least two clock domains
10/25/1995EP0550457A4 Fault tolerant computer system
10/24/1995US5461723 Dual channel data block transfer bus
10/24/1995US5461721 System for transferring data between I/O devices and main or expanded storage under dynamic control of independent indirect address words (IDAWs)
10/24/1995US5461720 System for increasing the efficiency of communications between controller and plurality of host computers by prohibiting retransmission of the same message for predetermined period of time
10/24/1995US5461717 Apparatus for transferring data between a host device and portable computers of various sizes and for recharging the batteries of same
10/24/1995US5461705 Information processing device in an electronic apparatus utilizing an accessory control device and methods of application
10/24/1995US5461701 System and method for peripheral data transfer
10/24/1995US5461330 Bus settle time by using previous bus state to condition bus at all receiving locations
10/24/1995CA2069779C Video teleconferencing system
10/24/1995CA2046720C Nonsynchronous channel/dasd communication system
10/24/1995CA2046489C Fault processing system for processing faults of producing points
10/19/1995WO1995027943A1 Device for interconnecting computer equipment using heterogeneous communication systems, and key therefor
10/19/1995DE4412706A1 Image bus system for processor network
10/19/1995DE19514696A1 Serial bus connection equipment eliminating functional interference
10/18/1995EP0677946A2 Data transfer control method and information processing system using the same
10/18/1995EP0677943A2 A communications system for exchanging data between computers in a network
10/18/1995EP0677940A2 Handoff monitoring in cellular communication network using slow frequency hopping
10/18/1995EP0677810A1 Combination of terminator apparatus enhancements
10/18/1995EP0677191A1 Method and apparatus for transmitting nrz data signals across an isolation barrier disposed in an interface between adjacent devices on a bus
10/17/1995US5459872 Software control of hardware interruptions
10/17/1995US5459870 In a computer system
10/17/1995US5459869 Method for providing protected mode services for device drivers and other resident software
10/17/1995US5459867 Kernels, description tables, and device drivers
10/17/1995US5459858 Method for file transfer
10/17/1995US5459856 System having independent access paths for permitting independent access from the host and storage device to respective cache memories
10/17/1995US5459846 Computer architecture system having an imporved memory
10/17/1995US5459844 In a digital computer system
10/17/1995US5459842 System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory
10/17/1995US5459840 Input/output bus architecture with parallel arbitration
10/17/1995US5459839 System and method for managing queue read and write pointers
10/17/1995US5459838 I/O access method for using flags to selectively control data operation between control unit and I/O channel to allow them proceed independently and concurrently
10/17/1995US5459660 Circuit and method for interfacing with vehicle computer
10/17/1995US5459579 Multifunctional document processing system for receiving document signals from a local or a remote device
10/17/1995US5459487 For a personal computer
10/17/1995US5459453 Integrated I/O interface device and connector module
10/17/1995US5459429 Drive for a symmetrical bipolar transistor
10/17/1995US5459413 Bus interfacing circuit for a FIFO memory
10/17/1995CA2044522C Apparatus and method for loading a system reference diskette image from a system partition in a personal computer system
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