| Patents for G06F 13 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (158,002) |
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| 09/26/1995 | US5454081 Expansion bus type determination apparatus |
| 09/26/1995 | US5454079 For transmitting messages on a network |
| 09/26/1995 | US5454078 System for sharing name among network adapters by, dynamically linking adapters having same logical name and maintaining linked state of remaining adapters |
| 09/26/1995 | US5453983 Port controller |
| 09/26/1995 | US5453779 Scheduling policies with grouping for providing VCR control functions in a video server |
| 09/26/1995 | CA2046664C Automated enrollment of a computer system into a service network of computer systems |
| 09/25/1995 | CA2145427A1 Correction for overlapping of start codes during token generation in a data pipeline system |
| 09/25/1995 | CA2145426A1 Pipeline processing machine, related system and multi-standard decoder including reconfigurable processing stages and method relating thereto |
| 09/25/1995 | CA2145424A1 Video formatting apparatus and decoder system and methods relating thereto |
| 09/25/1995 | CA2145423A1 Inverse modeller, system including same, and methods relating thereto |
| 09/25/1995 | CA2145225A1 Token technique in a pipelined video decompression system |
| 09/25/1995 | CA2145224A1 Apparatus for providing time delay to compressed video information and method relating thereto |
| 09/25/1995 | CA2145221A1 System and apparatus for decoding variable-length video data and methods relating thereto |
| 09/25/1995 | CA2145220A1 Decoder and video apparatus including token generator and methods relating thereto |
| 09/25/1995 | CA2145159A1 Method and apparatus for an inverse quantiser |
| 09/25/1995 | CA2145158A1 Multiple stage pipeline processor including reconfigurable processing stage for processing data having different standards and universal adaptation units and methods relating thereto |
| 09/25/1995 | CA2145157A1 Token technique in a pipelined video decompression system |
| 09/25/1995 | CA2145156A1 Spatial decoder and pipeline machine including same |
| 09/22/1995 | CA2143495A1 Method and apparatus for reordering incoming interleaved asynchronous transfer mode cells |
| 09/21/1995 | WO1995025311A1 System and method for communication with a remote network device |
| 09/21/1995 | WO1995025310A1 A peripheral processor card for upgrading a computer |
| 09/21/1995 | WO1995025309A1 Methods and apparatus for translating incompatible bus transactions |
| 09/21/1995 | WO1995025024A1 Method of cyclically transferring data between at least two separately operating control apparatus |
| 09/21/1995 | WO1995022094A3 Sorting sequential data prior to distribution over parallel processors in random access manner |
| 09/21/1995 | DE4408488A1 Verfahren zur zyklischen Übertragung von Daten zwischen mindestens zwei verteilt arbeitenden Steuergeräten Method for cyclic transmission of data between at least two distributed operating control devices |
| 09/21/1995 | DE19507780A1 Distributed image processing system using server client |
| 09/20/1995 | EP0681718A4 System for dividing processing tasks into signal processor and decision-making microprocessor interfacing. |
| 09/20/1995 | EP0673159A1 Scheduling policies with grouping for providing VCR control functions in a video server |
| 09/20/1995 | EP0672987A2 Portable PCMCIA interface for a host computer |
| 09/20/1995 | EP0672985A1 Asynchronous remote data duplexing |
| 09/20/1995 | EP0672980A2 Keyboard-touchpad combination in a bivalve enclosure |
| 09/20/1995 | EP0672282A1 Concurrent framework system. |
| 09/20/1995 | EP0672274A1 Computer network extender |
| 09/20/1995 | EP0525068A4 Integrated circuit i/o using a high preformance bus interface |
| 09/19/1995 | US5452470 Use of video RAM in high speed data communications |
| 09/19/1995 | US5452469 Command performing order change over system based on information contained in executed command in a data processor |
| 09/19/1995 | US5452462 Global communication interrupt control system for communication between real and virtual machine systems using global communication functions of a shared memory |
| 09/19/1995 | US5452460 Method and apparatus for creating secure pseudo-terminal links |
| 09/19/1995 | US5452455 Method of reconfiguring an input/output subsystem |
| 09/19/1995 | US5452450 System of global update for time/language heterogeneous databases using a relational reference database and both request and database identifier files |
| 09/19/1995 | US5452447 Computer system |
| 09/19/1995 | US5452436 System for connecting plurality of electronic units to data and clock buses wherein transmitting and receiving data in synchronization with transmitting and receiving clock signals |
| 09/19/1995 | US5452433 Common agent computer management system and method |
| 09/19/1995 | US5452432 Partially resettable, segmented DMA counter |
| 09/19/1995 | US5452424 Computer implemented method |
| 09/19/1995 | US5452422 Bus competitive control apparatus |
| 09/19/1995 | US5452421 System for using register sets and state machines sets to communicate between storage controller and devices by using failure condition activity defined in a request |
| 09/19/1995 | US5452420 Intelligent network interface circuit for establishing communication link between protocol machine and host processor employing counter proposal set parameter negotiation scheme |
| 09/19/1995 | US5452418 Method of using stream buffer to perform operation under normal operation mode and selectively switching to test mode to check data integrity during system operation |
| 09/19/1995 | US5452303 Communication apparatus comprising a local processor for processing a broadcast frame |
| 09/19/1995 | US5452289 Computer-based multifunction personal communications system |
| 09/15/1995 | CA2143492A1 Portable pcmcia interface for a host computer |
| 09/14/1995 | WO1995024803A1 Telecommunications switch with improved redundancy |
| 09/14/1995 | WO1995024787A1 Bi-directional data transmission device |
| 09/14/1995 | WO1995024729A2 Modular architecture for high bandwidth computers |
| 09/14/1995 | WO1995024685A1 System and method for efficient caching in a distributed file system |
| 09/14/1995 | WO1995024678A2 Highly pipelined bus architecture |
| 09/14/1995 | DE4407991A1 Einrichtung zur bidirektionalen Übertragung von Daten Means for bidirectional transmission of data |
| 09/13/1995 | EP0671828A1 Method and apparatus for improving the apparent accuracy of a data receiver clock circuit |
| 09/13/1995 | EP0671826A1 Device for optical transmissions |
| 09/13/1995 | EP0671719A1 Transfer processor with transparency |
| 09/13/1995 | EP0671718A1 Guided transfer line drawing |
| 09/13/1995 | EP0671693A1 Output buffer circuit having power down capability |
| 09/13/1995 | EP0671692A1 Fast pipelined distributed arbitration scheme |
| 09/13/1995 | EP0671691A2 Storage controller and bus control method for use therewith |
| 09/13/1995 | EP0671686A1 Synchronous remote data duplexing |
| 09/13/1995 | EP0671095A1 New d2b device address initialisation starts with previous address |
| 09/13/1995 | EP0671033A1 Arrangement for transmitting data over a bus |
| 09/12/1995 | US5450603 SIMD architecture with transfer register or value source circuitry connected to bus |
| 09/12/1995 | US5450602 Two stage register for capturing asynchronous events and subsequently providing them to a processor without loss or duplication of the captured events |
| 09/12/1995 | US5450591 Channel selection arbitration |
| 09/12/1995 | US5450583 Object-oriented language processing system |
| 09/12/1995 | US5450579 Method and apparatus for error recovery in computer peripheral devices |
| 09/12/1995 | US5450572 Method for transferring data between two data processing units |
| 09/12/1995 | US5450571 Dialog filtering process for a printing system to filter out non-selectable print programming selections |
| 09/12/1995 | US5450564 Method and apparatus for cache memory access with separate fetch and store queues |
| 09/12/1995 | US5450552 Expanded address bus system for providing address signals to expanding devices |
| 09/12/1995 | US5450551 System direct memory access (DMA) support logic for PCI based computer system |
| 09/12/1995 | US5450548 Apparatus for performing data transfer synchronously or asynchronously between device channels |
| 09/12/1995 | US5450547 Bus interface using pending channel information stored in single circular queue for controlling channels of data transfer within multiple FIFO devices |
| 09/12/1995 | US5450542 Bus interface with graphics and system paths for an integrated memory system |
| 09/12/1995 | US5450530 High speed receiver/transmitter interface |
| 09/12/1995 | US5450416 Apparatus and method for testing multifunction communications networks |
| 09/07/1995 | DE4406999A1 Differential bus driver circuit for vehicle bus system |
| 09/06/1995 | EP0670652A1 Improved graphical user interface for interactive television and video on demand |
| 09/06/1995 | EP0670553A1 Procedure for interleaved data transfers between a computer memory and peripheral equipment comprising a management system and several storage units |
| 09/06/1995 | EP0670551A1 Remote dual copy system |
| 09/06/1995 | EP0670546A2 Computer having operating system definition file for configuring computer system |
| 09/05/1995 | US5448743 General I/O port interrupt mechanism |
| 09/05/1995 | US5448742 Method and apparatus for local memory and system bus refreshing with single-port memory controller and rotating arbitration priority |
| 09/05/1995 | US5448724 Data processing system having double supervising functions |
| 09/05/1995 | US5448723 Method and apparatus for fault tolerant connection of a computing system to local area networks |
| 09/05/1995 | US5448715 Dual clock domain interface between CPU and memory bus |
| 09/05/1995 | US5448714 Sequential-access and random-access dual-port memory buffer |
| 09/05/1995 | US5448709 Disk array controller having command descriptor blocks utilized by bus master and bus slave for respectively performing data transfer operations |
| 09/05/1995 | US5448708 System for asynchronously delivering enqueue and dequeue information in a pipe interface having distributed, shared memory |
| 09/05/1995 | US5448706 Address generator for multi-channel circular-buffer style processing |
| 09/05/1995 | US5448704 Method for performing writes of non-contiguous bytes on a PCI bus in a minimum number of write cycles |
| 09/05/1995 | US5448703 Method and apparatus for providing back-to-back data transfers in an information handling system having a multiplexed bus |
| 09/05/1995 | US5448702 Adapters with descriptor queue management capability |