Patents
Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539)
04/1993
04/07/1993EP0535820A2 Method and apparatus for a register providing atomic access to set and clear individual bits of shared registers without software interlock
04/07/1993EP0535701A1 Architecture and method for combining static cache memory and dynamic main memory on the same chip (CDRAM)
04/07/1993EP0535670A1 Burst read address generation
04/07/1993EP0535538A1 Computer system with controller to prevent access to non-existent addresses
04/07/1993EP0535537A2 Computer system with a cache memory
04/07/1993EP0535218A1 Illumination system and method for a high definition light microscope
04/07/1993EP0535157A1 Method and apparatus for storing text data in subcode packs
04/07/1993EP0535107A1 Method for optimizing instruction scheduling
04/07/1993EP0535086A1 Multiple error correction in a computer memory.
04/06/1993US5201058 Control system for transferring vector data without waiting for transfer end of the previous vector data
04/06/1993US5201055 Multiprocessing system includes interprocessor encoding and decoding logic used for communication between two cards through reduced addressing lines
04/06/1993US5201052 System for transferring first and second ring information from program status word register and store buffer
04/06/1993US5201047 Attribute-based classification and retrieval system
04/06/1993US5201044 Data processing method for file status recovery includes providing a log file of atomic transactions that may span both volatile and non volatile memory
04/06/1993US5201041 Cache bypass apparatus
04/06/1993US5201036 Data processor having wait state control unit
04/06/1993US5200959 Device and method for defect handling in semi-conductor memory
04/06/1993CA1315896C Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage
04/06/1993CA1315891C2 Multitask subscription data retrieval system
04/05/1993CA2079564A1 Burst read address generation
04/04/1993CA2079690A1 Architecture and method for combining static cache memory and dynamic main memory on the same chip (cdram)
04/01/1993WO1993006661A1 Fast data compressor with direct lookup table indexing into history buffer
04/01/1993WO1993006552A1 Random access compare array
04/01/1993WO1993004429A3 Method of generating multidimensional addresses in an imaging and graphics processing system
03/1993
03/31/1993EP0534665A2 Fault containment system for multiprocessor with shared memory
03/31/1993EP0533813A1 Method for representing scalar data dependencies for an optimizing compiler
03/31/1993EP0533805A1 Method for efficient non-virtual main memory management
03/31/1993EP0288479B1 Apparatus and method for providing distributed control in a main memory unit of a data processing system
03/30/1993US5198804 Video memory with write mask from vector or direct input
03/30/1993CA1315411C Symmetric multi-processing control arrangement
03/30/1993CA1315409C Memory diagnostic apparatus and method
03/30/1993CA1315400C Exactly-once semantics in a tp queuing system
03/24/1993EP0533608A2 Method and apparatus for ensuring the recoverability of vital data in a data processing system
03/24/1993EP0533447A2 Digital data processor with improved paging
03/24/1993EP0533427A1 Computer memory control system
03/24/1993EP0533407A2 Heterogeneous transaction coordination
03/24/1993EP0533375A2 Computer system having memory testing means
03/24/1993EP0533374A1 Cache memory system
03/24/1993EP0533373A2 Computer system having cache memory
03/24/1993EP0533190A2 Data processing system with address translation function for different page sizes
03/24/1993EP0532690A1 Method and apparatus for managing page zero memory accesses in a multi-processor system
03/24/1993EP0532643A1 Method for optimizing software for any one of a plurality of variant architectures
03/24/1993CA2078311A1 Fault containment system for multiprocessor with shared memory
03/23/1993US5197148 Method for maintaining data availability after component failure included denying access to others while completing by one of the microprocessor systems an atomic transaction changing a portion of the multiple copies of data
03/23/1993US5197146 Method for maintaining cache coherence in a multiprocessor computer system
03/23/1993US5197145 Buffer storage system using parallel buffer storage units and move-out buffer registers
03/23/1993US5197144 Data processor for reloading deferred pushes in a copy-back data cache
03/23/1993US5197143 Device and method for distributing information in a computer system
03/23/1993US5197139 Cache management for multi-processor systems utilizing bulk cross-invalidate
03/23/1993US5197134 Pipeline processor for performing write instruction by referring to cache memory search result obtained during idling state of operand reading cycle
03/23/1993US5197130 Cluster architecture for a highly parallel scalar/vector multiprocessor system
03/23/1993US5197070 Scan register and testing circuit using the same
03/23/1993US5197001 Bill of material and project network processing
03/23/1993CA1315011C System for fast selection of non-cacheable address ranges using programmed array logic
03/23/1993CA1315010C Sequential access memory
03/23/1993CA1315005C Address generator with variable scan patterns
03/23/1993CA1315004C Instruction cache flush-on-rei control
03/21/1993CA2078312A1 Digital data processor with improved paging
03/21/1993CA2078310A1 Digital processor with distributed memory system
03/20/1993CA2078635A1 Data processing system
03/17/1993EP0532382A1 Method for management of structured objects
03/17/1993EP0532335A1 Maximising hit ratio in a data storage hierarchy
03/17/1993EP0532004A2 Method for manufacturing ROM type optical disk
03/17/1993EP0531784A2 Apparatus for encryption and decryption using split key
03/17/1993EP0531671A2 Memory card for computers, process for manufacturing this card and method of protecting software using the card
03/17/1993EP0531513A1 Improved adaptable performance evaluation device
03/17/1993EP0531431A1 Virtual processing address and instruction generator for parallel processor array
03/17/1993EP0531319A1 Dynamic information management computer system
03/17/1993EP0438556A4 Variable capacity cache memory
03/17/1993CN1070058A Dynamic enciphered method for single chip microcomputer program
03/16/1993US5195100 Non-volatile memory storage of write operation identifier in data sotrage device
03/16/1993US5195096 Method of functionally testing cache tag RAMs in limited-access processor systems
03/16/1993US5195089 Apparatus and method for a synchronous, high speed, packet-switched bus
03/11/1993DE4229286A1 Multiprocessor system with bus priority distribution for processor modules - has bus buffer drive control circuit using comparison of decoded addresses for system bus access control
03/11/1993CA2077285A1 Method for manufacturing rom type optical disk
03/10/1993EP0531243A1 Distributed crossbar switch architecture
03/10/1993EP0531194A1 Data authentication method
03/10/1993EP0531123A1 A dynamic address translation processing apparatus in a data processing system
03/10/1993EP0531079A1 Motor-operated window cover
03/10/1993EP0531004A2 Multiprocessor data processing with cross interrogate synchronization mechanism
03/10/1993EP0531003A1 Data processing with bidirectional data bus reservation priority controls
03/10/1993EP0530991A1 System and method for interleaving memory in a computer system
03/10/1993EP0530816A2 Microprocessor with cache memory and trace analyzer therefor
03/10/1993EP0530682A1 Method and means for addressing a very large memory
03/10/1993EP0530554A2 Scrubbing and sparing in a memory system
03/09/1993US5193202 Processor array with relocated operand physical address generator capable of data transfer to distant physical processor for each virtual processor while simulating dimensionally larger array processor
03/09/1993US5193192 Vectorized LR parsing of computer programs
03/09/1993US5193188 Centralized and distributed wait depth limited concurrency control methods and apparatus
03/09/1993US5193175 Fault-tolerant computer with three independently clocked processors asynchronously executing identical code that are synchronized upon each voted access to two memory modules
03/09/1993US5193173 Method and device for storing data subjected to dispersion processing
03/09/1993US5193172 Memory management system for dispatching only to a selected high-use-priority task a maximum allocated and given highest-use-priority real-pages when requested
03/09/1993US5193171 Method of managing space of peripheral storages and apparatus for the same
03/09/1993US5193170 Methods and apparatus for maintaining cache integrity whenever a cpu write to rom operation is performed with rom mapped to ram
03/09/1993US5193168 Multiprocessing system with enhanced shared storage
03/09/1993US5193166 Cache-memory architecture comprising a single address tag for each cache memory
03/09/1993US5193163 Two-level protocol for multi-component bus ownership, and implementation in a multi-processor cache write back protocol
03/09/1993US5193162 Cache memory with data compaction for use in the audit trail of a data processing system having record locking capabilities
03/09/1993US5193161 Computer system having mode independent addressing
03/09/1993US5193160 Address translation system with register storing section and area numbers
03/09/1993US5193150 Data transfer method, data transfer apparatus and information processing system