Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 12 - Accessing, addressing or allocating within memory systems or architectures
Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539)
06/1996
06/11/1996US5526504 For use in a processor that executes instructions
06/11/1996US5526503 Virtual addressing buffer circuit
06/11/1996US5526502 Memory interface
06/11/1996US5526501 Variable accuracy indirect addressing scheme for SIMD multi-processors and apparatus implementing same
06/11/1996US5526500 System for operand bypassing to allow a one and one-half cycle cache memory access time for sequential load and branch instructions
06/11/1996US5526482 Fault-tolerance storage device array
06/11/1996US5526364 Apparatus for entering and executing test mode operations for memory
06/11/1996US5526320 Burst EDO memory device
06/06/1996WO1996017354A1 Improved memory devices
06/06/1996WO1996017304A1 Bus-to-bus bridge
06/06/1996WO1996017300A1 Method for transforming a hash bucket number to a control interval to identify the physical location of information in a mass memory
06/06/1996WO1996017299A1 Scalar data cache for a vector processor
06/05/1996EP0715283A1 Security enclosure
06/05/1996EP0715252A1 A bit field peripheral
06/05/1996EP0715250A2 Method of processing input/output request in computer system including a plurality of subsystems
06/05/1996EP0715249A2 Methods of and system for reserving storage space for data migration in a redundant hierarchic data storage system by dynamically computing maximum storage space for mirror redundancy
06/05/1996EP0715247A1 System for controlling the distribution and use of digital works using digital tickets
06/05/1996EP0715246A1 System for controlling the distribution and use of composite digital works
06/05/1996EP0715245A1 System for controlling the distribution and use of digital works
06/05/1996EP0715244A1 System for controlling the distribution and use of digital works utilizing a usage rights grammar
06/05/1996EP0715243A1 System for controlling the distribution and use of digital works having a fee reporting mechanism
06/05/1996EP0714583A1 Method of transmitting teletext pages
06/05/1996EP0714536A1 Data bus
06/05/1996EP0714534A1 Multiple-port shared memory interface and associated method
06/05/1996DE4442957A1 Digital video data memory addressing circuit for MPEG video processing
06/05/1996CN1124001A A method and system for updating replicated databases in foreign and home telecommunication network systems for supporting global mobility of network
06/05/1996CN1123934A Multi-processor system, disk controller using the same and maintenance method thereof
06/05/1996CN1123933A Integrated level teo cache and memory controller with multiple data ports
06/05/1996CN1123932A Online placement of video files on disks in a server environment
06/05/1996CN1123931A Direct access structure of memory matched with bus bits
06/04/1996US5524269 System for activating and configuring an input/output board in a computer
06/04/1996US5524241 System and method for executing, tracking and recovering long running computations
06/04/1996US5524234 Coherency for write-back cache in a system designed for write-through cache including write-back latency control
06/04/1996US5524233 Method and apparatus for controlling an external cache memory wherein the cache controller is responsive to an interagent communication for performing cache control operations
06/04/1996US5524231 Nonvolatile memory card with an address table and an address translation logic for mapping out defective blocks within the memory card
06/04/1996US5524230 External information storage system with a semiconductor memory
06/04/1996US5524228 Memory control circuit for reducing the number of row address signals
06/04/1996US5524226 Register file system for microcomputer including a decoding system for concurrently activating source and destination word lines
06/04/1996US5524225 Cache system and method for providing software controlled writeback
06/04/1996US5524218 System for communicating data packets
06/04/1996US5524216 In a computing system
06/04/1996US5524214 System for modification of dynamic buffer allocation by comparing modification request with current allocation and updating allocation based upon comparison discrepancy
06/04/1996US5524212 Multiprocessor system with write generate method for updating cache
06/04/1996US5524208 Method and apparatus for performing cache snoop testing using DMA cycles in a computer system
06/04/1996US5524205 Data processing recovery apparatus
06/04/1996US5524203 Disk cache data maintenance system
06/04/1996US5524202 Method for forming graphic database and system utilizing the method
06/04/1996US5524190 Command object logging system for restoring documents
06/04/1996US5523703 Method and apparatus for controlling termination of current driven circuits
06/04/1996CA2026739C Transaction system security method and apparatus
05/1996
05/31/1996CA2160499A1 Bridge between buses in a system having a plurality of buses with different memory addressing capacities and having an arrangement for reallocating memory segments within the system memory map
05/30/1996WO1996016378A1 Active security device with electronic memory
05/30/1996WO1996016371A1 Method and structure for utilizing a dram array as second level cache memory
05/30/1996WO1996016370A1 Arrangement with a master unit and a plurality of slave units
05/30/1996WO1996008770A3 Register status protection during read-modify-write operation
05/30/1996DE4441752A1 Anordnung mit einer Master-Einheit und mehreren Slave-Einheiten Arrangement with a master and several slave units
05/29/1996EP0714076A1 Portable object with an electronic circuit powered by internal battery and with a data memory, method and device for externally powering this object and data transmission with the latter
05/29/1996EP0714066A2 Communications system and method including energy-efficient caching for mobile computing
05/29/1996EP0714065A1 Interface between a memory comprising a given number of address inputs and a processor having fewer address outputs, and processor and memory equipped therewith
05/29/1996EP0714061A2 Method of loading instructions into an instruction cache
05/29/1996EP0714060A1 One chip microcomputer with built-in non-volatile memory
05/28/1996US5522086 Software configurable ISA bus card interface with security access read and write sequence to upper data bits at addresses used by a game device
05/28/1996US5522077 Object oriented network system for allocating ranges of globally unique object identifiers from a server process to client processes which release unused identifiers
05/28/1996US5522075 Protection ring extension for computers having distinct virtual machine monitor and virtual machine address spaces
05/28/1996US5522069 Symmetric multiprocessing system with unified environment and distributed system functions
05/28/1996US5522068 In a computer system
05/28/1996US5522067 Working storage management in medical imaging systems
05/28/1996US5522064 Data processing apparatus for dynamically setting timings in a dynamic memory system
05/28/1996US5522062 Personal computer for accessing two types of extended memories having different memory capacities
05/28/1996US5522059 Apparatus for multiport memory access control unit with plurality of bank busy state check mechanisms employing address decoding and coincidence detection schemes
05/28/1996US5522058 Distributed shared-memory multiprocessor system with reduced traffic on shared bus
05/28/1996US5522057 Hybrid write back/write through cache having a streamlined four state cache coherency protocol for uniprocessor computer systems
05/28/1996US5522056 Cache memory with plurality of congruence sets and sense amplifiers shared among the congruence sets
05/28/1996US5522049 Semiconductor disk device with attachable integrated circuit cards
05/28/1996US5522045 Method for updating value in distributed shared virtual memory among interconnected computer nodes having page table with minimal processor involvement
05/28/1996US5522044 Networked facilities management system
05/28/1996US5522037 Backup control apparatus and method of data processing system
05/28/1996US5522032 Method of writing new data to discs
05/28/1996US5522027 In a computer system
05/28/1996US5521878 Clock synchronous semiconductor memory device
05/28/1996US5521849 System for operating application software in a safety critical environment
05/28/1996CA2020385C Memory subsystem input queue
05/23/1996WO1996015501A1 Object oriented database management system
05/23/1996CA2204733A1 Object oriented database management system
05/23/1996CA2163397A1 Portable object comprising an internal battery-powered electronici circuit and a data memory, external feeding process and device therefor and process for data transfer therewith
05/22/1996EP0713185A1 Database dependency resolution method and system for identifying related data files
05/22/1996EP0713183A2 Network independent file shadowing
05/22/1996EP0713181A1 Data processing system including mechanism for storing address tags
05/22/1996EP0713173A1 Data processing system
05/22/1996CN1122985A Video optimized dmedia streamer with distributed video data storage
05/21/1996US5519876 Processor communications bus having address lines selecting different storage locations based on selected control lines
05/21/1996US5519871 Data save apparatus for a battery-powered data processing unit
05/21/1996US5519869 Multi-density data storage backup allowing bootstrap image storage in density required by initial boot code and other system images at higher densities
05/21/1996US5519855 Summary catalogs
05/21/1996US5519853 Method and apparatus for enhancing synchronous I/O in a computer system with a non-volatile memory and using an acceleration device driver in a computer operating system
05/21/1996US5519847 Computer implemented method
05/21/1996US5519846 Multiprocessor system with scheme for managing allocation and reservation of cache segments in a cache system employing round-robin replacement and exclusive access
05/21/1996US5519845 Method and system for storage and retrieval of iterative data associated with an iterative process within a cache
05/21/1996US5519844 Logical partitioning of a redundant array storage system
05/21/1996US5519843 Flash memory system providing both BIOS and user storage capability
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