| Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539) |
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| 07/16/1996 | US5537635 Method and system for assignment of reclaim vectors in a partitioned cache with a virtual minimum partition size |
| 07/16/1996 | US5537632 Method and system for fault coverage testing memory |
| 07/16/1996 | US5537621 Integrated memory, method for managing it, and resultant information processing system |
| 07/16/1996 | US5537609 Mini cache operational module for enhancement to general cache |
| 07/16/1996 | US5537598 System for installing processor control code |
| 07/16/1996 | US5537595 Device management system in a computer system |
| 07/16/1996 | US5537592 System and method for reading and writing disks formatted for an operating system foreign to the host computer |
| 07/16/1996 | US5537588 Partitioned log-structured file system and methods for operating the same |
| 07/16/1996 | US5537585 Data storage management for network interconnected processors |
| 07/16/1996 | US5537581 Microprocessor with a core that operates at multiple frequencies |
| 07/16/1996 | US5537577 Interleaved memory wherein plural memory means comprising plural banks output data simultaneously while a control unit sequences the addresses in ascending and descending directions |
| 07/16/1996 | US5537576 Expandable memory for a digital signal processor including mapped first and second memory banks forming a continuous and contiguous address space |
| 07/16/1996 | US5537575 In a computer system |
| 07/16/1996 | US5537574 Sysplex shared data coherency method |
| 07/16/1996 | US5537573 Cache system and method for prefetching of data |
| 07/16/1996 | US5537572 Cache controller and method for dumping contents of a cache directory and cache data random access memory (RAM) |
| 07/16/1996 | US5537571 Control device for a buffer memory with reconfigurable partitioning |
| 07/16/1996 | US5537570 Cache with a tag duplicate fault avoidance system and method |
| 07/16/1996 | US5537569 Multiprocessor system utilizing a directory memory and including grouped processing elements each having cache |
| 07/16/1996 | US5537568 System for dynamically controlling cache manager maintaining cache index and controlling sequential data access |
| 07/16/1996 | US5537567 Parity block configuration in an array of storage devices |
| 07/16/1996 | US5537565 Dynamic memory system having memory refresh |
| 07/16/1996 | US5537564 Technique for accessing and refreshing memory locations within electronic storage devices which need to be refreshed with minimum power consumption |
| 07/16/1996 | US5537555 Fully pipelined and highly concurrent memory controller |
| 07/16/1996 | US5537553 Method for controlling communication between internal buses |
| 07/16/1996 | US5537526 Method and apparatus for processing a display document utilizing a system level document framework |
| 07/16/1996 | US5537361 Semiconductor memory device and memory access system using a four-state address signal |
| 07/16/1996 | CA2053741C Access security integrated circuit |
| 07/11/1996 | WO1996021297A1 Method and apparatus for securing data stored in semiconductor memory cells |
| 07/11/1996 | WO1996021186A2 Plural multiport register file to accommodate data of differing lengths |
| 07/10/1996 | CN1126339A Video data bus communication system and method |
| 07/09/1996 | US5535409 Apparatus for and method of preventing changes of computer configuration data by unauthorized users |
| 07/09/1996 | US5535404 Microprocessor status register having plural control information registers each set and cleared by on and off decoders receiving the same control data word |
| 07/09/1996 | US5535390 In a computer system |
| 07/09/1996 | US5535385 Dealing with side effects of transactions in data base systems using a multi-set algebra |
| 07/09/1996 | US5535375 Computer |
| 07/09/1996 | US5535369 Method for allocating memory in a solid state memory disk |
| 07/09/1996 | US5535368 Automatically-configuring memory subsystem |
| 07/09/1996 | US5535364 Adaptive method for dynamic allocation of random access memory to procedures having differing priorities based on first and second threshold levels of free RAM |
| 07/09/1996 | US5535363 Computer system |
| 07/09/1996 | US5535361 Cache block replacement scheme based on directory control bit set/reset and hit/miss basis in a multiheading multiprocessor environment |
| 07/09/1996 | US5535360 Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor |
| 07/09/1996 | US5535359 Computer system with cache memory having address mask register |
| 07/09/1996 | US5535358 Cache memory control circuit and method for controlling reading and writing requests |
| 07/09/1996 | US5535357 Flash memory system providing both BIOS and user storage capability |
| 07/09/1996 | US5535353 Address generating circuit for data compression |
| 07/09/1996 | US5535352 Computing system |
| 07/09/1996 | US5535351 Address translator with by-pass circuit and method of operation |
| 07/09/1996 | US5535350 Cache memory unit including a replacement address register and address update circuitry for reduced cache overhead |
| 07/09/1996 | US5535349 Data processing system and method for providing chip selects to peripheral devices |
| 07/09/1996 | US5535332 Shared-data alteration status management apparatus |
| 07/09/1996 | US5535328 Method of operating a computer system |
| 07/09/1996 | US5535312 Apparatus and method for managing memory in a printing system |
| 07/09/1996 | US5535226 Memory device employing error correction |
| 07/09/1996 | US5535173 Data-storage device |
| 07/09/1996 | US5535170 Sequential access memory that can have circuit area reduced |
| 07/09/1996 | US5535162 Electrically erasable read only memory |
| 07/09/1996 | US5535116 Flat cache-only multi-processor architectures |
| 07/09/1996 | US5535063 System for providing random access to a data set |
| 07/09/1996 | US5534855 Method and system for certificate based alias detection |
| 07/09/1996 | CA2035876C Computer with cache |
| 07/09/1996 | CA2011632C Partially storing control circuit used in a memory unit |
| 07/04/1996 | WO1996020481A1 Distributed write data drivers for burst access memories |
| 07/04/1996 | WO1996020480A1 System adapted to receive multiple memory types |
| 07/04/1996 | WO1996020479A1 Burst edo memory device address counter |
| 07/04/1996 | WO1996020478A1 Synchronous burst extended data out dram |
| 07/04/1996 | WO1996020477A1 Burst edo memory device with maximized write cycle timing |
| 07/04/1996 | WO1996020446A1 Main memory system with multiple data paths |
| 07/03/1996 | EP0720362A2 Television on-screen display system utilizing text data compression |
| 07/03/1996 | EP0720336A2 Script preprocessing system and method |
| 07/03/1996 | EP0720166A2 Data reproducing device |
| 07/03/1996 | EP0720098A1 Apparatus for securing information systems organised around microprocessors |
| 07/03/1996 | EP0720096A2 Apparatus and method for providing continuity of operation in a system |
| 07/03/1996 | EP0720091A2 Multi-level token management for distributed file systems |
| 07/03/1996 | EP0720087A1 Apparatus and method for a memory extension stack in a data processing system |
| 07/03/1996 | EP0719485A1 Access control for portable data storage media |
| 07/03/1996 | CN1125991A A method of attaining data access in a primary memory based database |
| 07/02/1996 | US5533187 Multiple block mode operations in a frame buffer system designed for windowing operations |
| 07/02/1996 | US5533126 Key protection device for smart cards |
| 07/02/1996 | US5533125 Removable computer security device |
| 07/02/1996 | US5533035 Error detection and correction method and apparatus |
| 07/02/1996 | US5532954 Single in-line memory module |
| 07/02/1996 | US5532920 Data processing system and method to enforce payment of royalties when copying softcopy books |
| 07/02/1996 | CA2009548C Single physical main storage shared by two or more processors executing respective operating systems |
| 06/27/1996 | WO1996019894A1 Television set with a plurality of signal processing devices |
| 06/27/1996 | WO1996019818A1 A cache sram connector assembly |
| 06/27/1996 | WO1996019809A2 Method of and device for writing and reading data items in a memory system |
| 06/27/1996 | WO1996019793A1 Memory bandwidth optimization |
| 06/27/1996 | DE4445803A1 Fernsehgerät TV |
| 06/27/1996 | DE4445801A1 Dynamic RAM memory drive circuit |
| 06/26/1996 | EP0718838A2 Security check method for a game device |
| 06/26/1996 | EP0718794A1 Method and device for increasing the security of an integrated circuit |
| 06/26/1996 | EP0718783A1 A computer implemented method and system for information retrieval |
| 06/26/1996 | EP0718779A1 Single-chip microcomputer |
| 06/26/1996 | EP0718775A1 Reading from and writing to a m-byte memory utilizing a processor having a n-byte data bus |
| 06/26/1996 | EP0718769A1 Apparatus for memory word access protection |
| 06/26/1996 | EP0718768A1 Single-chip microcomputer |
| 06/26/1996 | EP0718759A2 System for managing hierarchical information in a digital data processing system |
| 06/26/1996 | EP0718756A1 Security system for software |
| 06/26/1996 | EP0424407B1 Intermediate spreadsheet structure |