Patents
Sitemap › G06 - Computing; Calculating; Counting › G06F - Electric digital data processing › G06F 12 - Accessing, addressing or allocating within memory systems or architectures
Patents for G06F 12 - Accessing, addressing or allocating within memory systems or architectures (152,539)
10/1996
10/15/1996US5566324 Computer apparatus including a main memory prefetch cache and method of operation thereof
10/15/1996US5566323 Data processing system including programming voltage inhibitor for an electrically erasable reprogrammable nonvolatile memory
10/15/1996US5566321 Method of managing distributed memory within a massively parallel processing system
10/15/1996US5566319 System and method for controlling access to data shared by a plurality of processors using lock files
10/15/1996US5566318 Circuit with a single address register that augments a memory controller by enabling cache reads and page-mode writes
10/15/1996US5566317 Method and apparatus for computer disk drive management
10/15/1996US5566315 Process of predicting and controlling the use of cache memory in a computer system
10/15/1996US5566314 Flash memory device employing unused cell arrays to update files
10/15/1996US5566313 Apparatus for controlling the transfer of data
10/15/1996US5566312 Processimg unit with programmable mis-aligned byte addressing
10/15/1996US5566311 Semiconductor memory controller for reducing pass through current
10/15/1996US5566309 Variable memory boundaries between external and internal memories for single-chip microcomputer
10/15/1996US5566131 Memory circuit for display apparatus
10/15/1996US5566118 Dynamic semiconductor memory device with sense amplifiers as cache memories
10/15/1996US5566068 Method in a computer system
10/15/1996CA2173908A1 Protection system for critical memory information
10/15/1996CA2173695A1 Method and system for providing interoperability among processes written to execute on different operating systems
10/10/1996WO1996031827A1 A modular bus with single or double parallel termination
10/10/1996WO1996031825A1 Memory management
10/09/1996EP0736846A2 Microprocessor systems for electronic postage arrangements
10/09/1996EP0736834A2 Hyper text system and its display method
10/09/1996EP0736829A2 Variable computer icon for single control of complex software functions executed on a data processing system
10/09/1996EP0735975A1 Ophthalmic package and delivery device
10/08/1996US5564113 Computer program product for rendering relational database management system differences transparent
10/08/1996US5564111 Method and apparatus for implementing a non-blocking translation lookaside buffer
10/08/1996US5564055 PCMCIA slot expander and method
10/08/1996US5564052 Logically disconnectable virtual-to-physical address translation unit and method for such disconnection
10/08/1996US5564046 Method and system for creating a database by dividing text data into nodes which can be corrected
10/08/1996US5564037 Real time data migration system and method employing sparse files
10/08/1996US5564036 Memory protective circuit
10/08/1996US5564035 Exclusive and/or partially inclusive extension cache system and method to minimize swapping therein
10/08/1996US5564034 Cache memory with a write buffer indicating way selection
10/08/1996US5564032 Control apparatus for controlling memory unit capable of selecting an electrically erasable non-volatile memory and loading information stored therein
10/08/1996US5564030 Circuit and method for detecting segment limit errors for code fetches
10/08/1996US5564029 Pipeline processor which avoids resource conflicts
10/08/1996US5563950 System and methods for data encryption using public key cryptography
10/08/1996US5563948 Process for authentication of smart cards, and device for use of the process
10/08/1996US5563947 Cd-prom
10/08/1996US5563946 Method and apparatus for enabling trial period use of software products: method and apparatus for passing encrypted files between data processing systems
10/08/1996US5563945 Data storage device
10/08/1996US5563894 Error detecting and correcting method and system
10/08/1996US5563878 Transaction message routing in digital communication networks
10/08/1996US5563833 Using one memory to supply addresses to an associated memory during testing
10/08/1996US5563395 Card type storage medium and card type storage medium issuing apparatus
10/08/1996CA2090567C Method of and apparatus for data distribution
10/08/1996CA1338639C Communication control device
10/03/1996WO1996030881A1 Smart card and method for enhancing the reliability of an application access request
10/03/1996WO1996030847A1 Method and apparatus for transaction processing in a distributed database system
10/03/1996WO1996030846A1 An integrated development platform for distributed publishing and management of hypermedia over wide area networks
10/03/1996WO1996030842A1 Bus structure for a multiprocessor system
10/03/1996WO1996030840A1 Method and means for interconnecting different security level networks
10/03/1996WO1996030839A1 Real time data migration system and method employing sparse files
10/03/1996WO1996030838A1 Memory controller which executes read and write commands out of order
10/03/1996WO1996030837A1 Upgradable, cpu portable multi-processor crossbar interleaved computer
10/03/1996WO1996030836A1 System and method using address prediction and cache replacement scheme with forced lru status
10/03/1996WO1996030824A1 Data backup method, mirror ring apparatus and its control
10/02/1996EP0735721A2 Method for master key generation and registration
10/02/1996EP0735720A2 Method for key distribution and verification in a key management system
10/02/1996EP0735719A2 Method for providing secure boxes in a key management system
10/02/1996EP0735491A2 DMA controller
10/02/1996EP0735489A1 Method of protecting zones of non-volatile memories
10/02/1996EP0735488A1 Multi-program execution controlling apparatus and method
10/02/1996EP0735487A2 A fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system
10/02/1996EP0735486A1 Packet switched cache coherent multiprocessor system
10/02/1996EP0735485A1 A parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system
10/02/1996EP0735484A1 A writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system
10/02/1996EP0735483A1 A transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system
10/02/1996EP0735482A1 A parallelized master request class structure for interfacing a processor in a packet switched cache coherent multiprocessor system
10/02/1996EP0735481A1 System level mechanism for invalidating data stored in the external cache of a processor in a computer system
10/02/1996EP0735480A1 Cache coherent computer system that minimizes invalidation and copyback operations
10/02/1996EP0735479A1 Cache memory to processor bus interface and method thereof
10/02/1996EP0735478A1 Variable configuration data processing system with automatic serial test interface connection configuration and bypass device
10/02/1996EP0735473A2 Method and apparatus for managing a database in a distributed object operating environment
10/02/1996EP0735465A1 Method and apparatus for providing transparent persistence in a distributed object operating environment
10/02/1996EP0735463A2 Computer processor having a register file with reduced read and/or write port bandwidth
10/02/1996EP0735456A2 System resource enable apparatus
10/02/1996EP0734626A1 Method of and apparatus for processing data at a remote workstation
10/02/1996EP0734553A1 Split level cache
10/02/1996EP0711479A4 Cd prom encryption system
10/02/1996EP0608329A4 Method and apparatus for creating a cd-rom disc for use with multiple operating systems.
10/02/1996CN1132564A Method and appts. for data storage and retrieval
10/02/1996CN1132372A Efficient and secure update of software and data
10/01/1996US5561818 Microprocessor and data processing system for data transfer using a register file
10/01/1996US5561814 Methods and apparatus for determining memory operating characteristics for given memory locations via assigned address ranges
10/01/1996US5561813 Circuit for resolving I/O port address conflicts
10/01/1996US5561799 Extensible file system which layers a new file system with an old file system to provide coherent file data
10/01/1996US5561797 Method for synchronizing transaction processing in a distributed heterogeneous system
10/01/1996US5561788 Method and system for executing programs using memory wrap in a multi-mode microprocessor
10/01/1996US5561786 Computer method and system for allocating and freeing memory utilizing segmenting and free block lists
10/01/1996US5561785 System for allocating and returning storage and collecting garbage using subpool of available blocks
10/01/1996US5561784 Interleaved memory access system having variable-sized segments logical address spaces and means for dividing/mapping physical address into higher and lower order addresses
10/01/1996US5561783 Dynamic cache coherency method and apparatus using both write-back and write-through operations
10/01/1996US5561782 In a computer system
10/01/1996US5561781 Port swapping for improved virtual SRAM performance and processing of concurrent processor access requests
10/01/1996US5561780 Method and apparatus for combining uncacheable write data into cache-line-sized write buffers
10/01/1996US5561779 Processor board having a second level writeback cache system and a third level writethrough cache system which stores exclusive state information for use in a multiprocessor computer system
10/01/1996US5561778 System for representing data object in concatenated multiple virtual address spaces with combined requests for segment mapping
10/01/1996US5561777 Process for sequentially reading a page from an image memory in either of two directions
10/01/1996US5561775 Parallel processing apparatus and method capable of processing plural instructions in parallel or successively
10/01/1996US5561767 Safety critical processor and processing method for a data processing system
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