Patents
Sitemap › H03 - Basic electronic circuitry › H03K - Pulse technique › H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass
Patents for H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass (25,714)
11/2000
11/21/2000US6150847 Device and method for generating a variable duty cycle clock
11/16/2000WO2000069070A1 Circuit arrangement and optical read/write device including the circuit arrangement
11/16/2000DE19929801C1 Integrated circuit e.g. for generation of phase-shifted output clock from clock signal
11/16/2000DE19918512C1 Schaltungsanordnung mit einer Reduktionsschaltung zur Reduktion von Störlängsspannungen auf einer Zweidrahtleitung Circuit arrangement with a reduction circuit for reducing Störlängsspannungen on a two-wire cable
11/16/2000DE19811868C2 Hochauflösende Verzögerungsschaltung High-resolution delay circuit
11/15/2000EP1051805A1 Self-calibrating programmable phase shifter
11/14/2000US6148025 System and method for compensating for baseline wander
11/14/2000US6147538 CMOS triggered NMOS ESD protection circuit
11/14/2000US6147536 Delay circuit for delaying a high frequency signal and capable of adjusting an effective pulse width
11/14/2000US6147533 Data communication receiving elements
11/14/2000US6147532 PLL circuit capable of preventing malfunction of FF circuits connected thereto and semiconductor integrated circuit including the PLL circuit
11/14/2000US6147529 Voltage sensing circuit
11/14/2000US6147527 Internal clock generator
11/14/2000US6147525 Frequency multiplier circuit operable with an external reference clock signal having a frequency in a wide range
11/14/2000US6147523 Overshoot control and damping circuit for high speed drivers
11/14/2000US6147519 Low-voltage comparator with wide input voltage swing
11/14/2000US6147518 Current comparator
11/14/2000US6147516 Power edge detector
11/09/2000WO2000067381A1 Frequency-multiplying delay locked loop
11/09/2000WO2000067378A1 Method and apparatus for a single event upset (seu) tolerant clock splitter
11/08/2000EP1050105A1 A pulse edge detector with double resolution
11/08/2000EP0927460B1 Steep edge time-delay relay
11/08/2000EP0897614B1 Clock signal generator
11/07/2000US6144713 Delay locked loop circuit for controlling delay time with reduced lock-up time
11/07/2000US6144649 Method and apparatus for acquiring a pilot signal in a CDMA receiver
11/07/2000US6144232 Chopper type voltage comparing circuit capable of correctly determining output polarity, and voltage comparing method
11/07/2000US6144223 Integrated circuit SCSI input receiver having precision high speed input buffer with hysteresis
11/07/2000US6144034 Delay calibration for gamma camera timing circuit
11/02/2000WO2000065717A1 Clock generation circuit, serial/parallel converter and parallel/serial converter, and semiconductor device
11/02/2000WO2000065716A1 Circuitry for a high voltage linear current sense ic
11/02/2000WO2000065651A1 Semiconductor integrated circuit
11/02/2000EP1049257A2 Phase selection circuit
11/02/2000EP1048108A1 A variable delay cell with a self-biasing load
11/02/2000DE19961135A1 Voltage detection circuit for use in semiconductor memory component, includes compensation current generation section for preventing potential of signalling line VPP from rising steeply
11/01/2000CN1058118C Signal controlled phase shifter
10/2000
10/31/2000US6141266 Method and apparatus for generating a signal with a voltage insensitive or controlled delay
10/31/2000US6140860 Thermal sensing circuit
10/31/2000US6140857 Method and apparatus for reducing baseline wander
10/31/2000US6140856 Parametric tuning of an intergrated circuit after fabrication
10/31/2000US6140835 Input buffer circuit
10/26/2000DE10000439A1 Pulse generating circuit includes delay circuit and invertor where outputs are input to AND circuit
10/25/2000EP1047220A2 Adjustable data delay using programmable clock shift
10/25/2000EP1047205A2 Circuit device having reduction circuit for reducing the crosstalk on a two-wire line
10/25/2000EP1047195A2 Delay locked loop and clock circuit using a delay locked loop
10/25/2000EP1047194A1 High-frequency clipping stage
10/25/2000CN1271212A Delay element using delay locking ring
10/24/2000US6138262 Memory address generator in convolutional interleaver/deinterleaver
10/24/2000US6137338 Low resistance input protection circuit
10/24/2000US6137336 Circuit and method for generating multiphase clock
10/24/2000US6137334 Logic circuit delay stage and delay line utilizing same
10/24/2000US6137333 Optimal delay controller
10/24/2000US6137328 Clock phase correction circuit
10/24/2000US6137327 Delay lock loop
10/24/2000US6137325 Device and methods in a delay locked loop for generating quadrature and other off-phase clocks with improved resolution
10/24/2000US6137319 Reference-free single ended clocked sense amplifier circuit
10/24/2000US6137309 Exclusive-or logic gate with four two-by-two complementary inputs and two complementary outputs, and frequency multiplier incorporating said gate
10/24/2000US6137306 Input buffer having adjustment function for suppressing skew
10/19/2000DE10009039A1 Clock period detection circuit for multiplier circuit, detects whether clock signal passes through detector or bypasses detector to output control signal, based on which clock period is detected
10/18/2000EP1045534A1 Method to determine the position of a constant frequency interval in a telecommunication signal
10/18/2000CN1270713A Master-salve delay locked loop for accurate delay of non-periodic signals
10/18/2000CN1270412A System and method for compensating parameter of crystal sheets
10/17/2000US6134279 Peak detector using automatic threshold control and method therefor
10/17/2000US6134252 Enhanced glitch removal circuit
10/17/2000US6134191 Oscillator for measuring on-chip delays
10/17/2000US6133861 Selectable delay circuit having immunity to variations in fabrication and operating condition for write precompensation in a read/write channel
10/17/2000US6133774 Clock generator and method therefor
10/17/2000US6133773 Variable delay element
10/17/2000US6133767 Digital driver circuit for an integrated circuit
10/17/2000US6133764 Comparator circuit and method
10/17/2000US6133751 Programmable delay element
10/11/2000EP1042867A1 Differential comparator with stable switching threshold
10/11/2000EP0998788A4 Pulse stuffing circuit for programmable delay line
10/11/2000EP0757857B1 Low-voltage cmos comparator
10/11/2000CN1269651A Method and system for synchronising multiple subsystems using a voltage-controlled oscillator
10/10/2000US6131168 System and method for reducing phase error in clocks produced by a delay locked loop
10/10/2000US6130567 Semiconductor delay circuit having inverter circuits and transfer gates
10/10/2000US6130566 Digital wave shaping circuit, frequency multiplying circuit, and external synchronizing method, and external synchronizing circuit
10/10/2000US6130565 Charge pump circuit, PLL circuit, and pulse-width modulation circuit
10/05/2000WO2000059113A1 Pulse clock/signal delay apparatus and method
10/05/2000WO2000059087A1 Time tolerance control unit
10/05/2000DE19910885A1 Schaltungsanordnung zum störungsfreien Initialisieren von Delay-Locked-Loop-Schaltungen mit Fast-Lock Circuitry for trouble-free initialization of delay-locked loop circuits with Fast-Lock
10/05/2000CA2365105A1 Pulse clock/signal delay apparatus and method
10/04/2000EP1041720A1 Binary zero determination signal generating circuit
10/04/2000EP1041718A2 A low power adjustable input threshold circuit
10/04/2000EP1041469A2 Method and apparatus for extending a resolution of a clock
10/04/2000EP1040578A1 A delay locked loop with harmonic lock detection
10/04/2000EP1040577A2 Detector for the recognition of missing impulses
10/04/2000EP1040400A1 Circuit for reducing input voltage
10/04/2000CN1269028A Interface circuit for full-custom and semi-custom timing domains
10/03/2000US6128248 Semiconductor memory device including a clocking circuit for controlling the read circuit operation
10/03/2000US6128170 Analog based first and fast second pulse removal system
10/03/2000US6127896 Phase locked loop having control circuit for automatically operating VCO on an optimum input/output characteristic
10/03/2000US6127872 Delay circuit and oscillator circuit using the same
10/03/2000US6127871 Variable digital delay line
10/03/2000US6127870 Output delay circuit
10/03/2000US6127869 Circuit for calibrating delay lines and method
10/03/2000US6127868 Timer circuit
10/03/2000US6127866 Delay-locked-loop (DLL) having symmetrical rising and falling clock edge type delays
10/03/2000US6127865 Programmable logic device with logic signal delay compensated clock network
10/03/2000US6127858 Method and apparatus for varying a clock frequency on a phase by phase basis
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