Patents
Patents for H03K 5 - Manipulating pulses not covered by one of the other main groups in this subclass (25,714)
10/2000
10/03/2000US6127854 Differential comparator with stable switching threshold
10/03/2000US6127840 Dynamic line termination clamping circuit
09/2000
09/28/2000WO2000057552A1 Delay stabilization system for an integrated circuit
09/28/2000WO2000057136A1 Detection of passing magnetic articles while adapting the detection threshold
09/28/2000DE10013553A1 Delay device for delaying incoming transmission signals in electronic instrument, has delay elements operating on power supply voltages, connected in series, and with a switch unit that outputs one of outputs of delay elements
09/27/2000EP1039644A2 Multi-level signal discriminator
09/27/2000EP1039638A1 Circuit for initialising fast-lock delay locked loop circuits without interference
09/27/2000EP1039637A1 Delay line with frequency range trimming
09/26/2000US6125157 Delay-locked loop circuitry for clock delay adjustment
09/26/2000US6125075 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions
09/26/2000US6124759 Comparator with a large input voltage excursion
09/26/2000US6124746 Adjustable delay circuit
09/26/2000US6124745 Delay and interpolation timing structures and methods
09/26/2000US6124744 Electronic circuit apparatus having circuits for effectively compensating for clock skew
09/26/2000US6124743 Reference voltage generation circuit for comparator
09/26/2000US6124739 Monolithically integrated signal processing circuit
09/26/2000US6124738 Input buffer for semiconductor device
09/21/2000WO2000055829A1 Jitter buffer and methods for control of same
09/21/2000DE19912632A1 Circuit for amplification and/or conversion of analog electrical signals in the form of voltages or currents using microprocessor controller to control the adjustment/alignment of individual functional region and components tolerance
09/19/2000US6122751 Pipelined data processing circuit
09/19/2000US6121913 Electronic system with high speed, low power, A/D converter
09/19/2000US6121912 Subranging analog-to-digital converter and method
09/19/2000US6121813 Delay circuit having a noise reducing function
09/19/2000US6121812 Delay circuit having delay time free from influence of operation environment
09/19/2000US6121811 Variable time delay circuit and method
09/19/2000US6121809 Accurate and tuneable active differential phase splitters in RFIC wireless applications
09/19/2000US6121808 DLL calibrated phase multiplexer and interpolator
09/19/2000US6121805 Universal duty cycle adjustment circuit
09/17/2000CA2300726A1 Signal processing circuit for a digital signal receiving system
09/14/2000WO2000054556A1 Circuit arrangement for operating a luminous element
09/14/2000WO2000054401A1 Method for generating a signal with adjustable frequency using a dither signal generator
09/13/2000CN1266496A Low cost CMOS tester with high channel density
09/13/2000CN1266495A Tester with fast refire recovery time
09/12/2000US6118830 Digital DC restoration device
09/12/2000US6118730 Phase comparator with improved comparison precision and synchronous semiconductor memory device employing the same
09/12/2000US6118390 Apparatus for obtaining a pulse width of an unknown pulse signal
09/12/2000US6118319 Timing signal generation circuit
09/12/2000US6118313 Digital frequency multiplying circuit
09/12/2000US6118312 Clock switch circuit
09/12/2000US6118308 Circuit configuration for a comparator
09/08/2000WO2000052822A1 Dual control analog delay element
09/07/2000DE19920335C1 Arrangement for phase matching of data signal to clock signal in digital integrated circuit, e.g. for mobile telephones and software radio
09/07/2000DE19905053A1 Komparatorschaltung Comparator
09/06/2000EP1033814A2 Integrated circuit for generating two non-overlapping clock signals
09/06/2000EP1033721A2 Programmable delay control in a memory
09/06/2000CN1265509A Programmable delay control for use in storage
09/05/2000US6115769 Method and apparatus for providing precise circuit delays
09/05/2000US6115439 Free running digital phase lock loop
09/05/2000US6115430 Differentiating circuit and clock generator circuit using the differentiating circuit
09/05/2000US6114915 Programmable wide-range frequency synthesizer
09/05/2000US6114891 Pulse generating circuit for dynamic random access memory device
09/05/2000US6114882 Current comparator and method therefor
09/05/2000US6114879 Phase detectors
09/05/2000US6114877 Timing circuit utilizing a clock tree as a delay device
09/05/2000CA2152855C Gtl edge rate control circuit
08/2000
08/31/2000DE19957613A1 Synchronizing element for converting an asynchronous pulse signal into a synchronous pulse signal has arrangement of interconnected flip-flops, AND gates and NAND gates
08/31/2000DE19907177A1 Verzögerungsschaltung Delay circuit
08/30/2000EP1031203A2 Delay locked loop circuitry for clock delay adjustment
08/29/2000US6111965 Method and apparatus for offset compensation of a signal processing circuit
08/29/2000US6111925 Clock synchronized delay scheme using edge-triggered delay lines and latches with one clock lock time
08/29/2000US6111796 Programmable delay control for sense amplifiers in a memory
08/29/2000US6111794 Memory interface circuit including bypass data forwarding with essentially no delay
08/29/2000US6111530 Method for detecting data output by optical coupler using analog to digital converter with preset initial reference
08/29/2000US6111468 Charge pump with charge/discharge amount control
08/29/2000US6111449 Clamping circuit for absorbing ringing of signal
08/29/2000US6111448 Clock signal distribution circuit
08/29/2000US6111447 Timing circuit that selectively triggers on a rising or falling input signal edge
08/29/2000US6111446 Integrated circuit data latch driver circuit
08/29/2000US6111445 Phase interpolator with noise immunity
08/29/2000US6111443 Accelerated switching by selection of various threshold levels
08/29/2000US6111437 Wide common-mode differential receiver with precision input referred offset
08/29/2000US6111436 Measurement of signal propagation delay using arbiters
08/24/2000WO2000049712A1 Delay circuit
08/23/2000CN1055812C Shifting the phase of clock signal for clock recovery of digital data signal and method thereof
08/22/2000US6108528 Receive squelch circuit having function of detecting pulse width
08/22/2000US6108266 Memory utilizing a programmable delay to control address buffers
08/22/2000US6107854 Variable speed path circuit and method
08/22/2000US6107850 Output pulse width control system
08/22/2000US6107846 Frequency multiplication circuit
08/22/2000US6107831 Level conversion circuit
08/17/2000WO2000048315A1 Comparator circuit
08/16/2000EP1028529A1 Synchronized data capturing circuits using reduced voltage levels and methods therefor
08/16/2000EP1028429A2 Prefetch architectures for data and timing signlas in an integrated circuit and methods therefor
08/16/2000EP1028369A2 System and method for automatic deskew across a high speed, parallel interconnection
08/16/2000EP0850482B1 Method and apparatus for detecting assertion of multiple signals
08/16/2000CN1263648A Device and method for generating time mean value-free binary signal
08/16/2000CN1263382A Time-delay phase-locked loop with symmetrical rising and dropping clock along type time delaying quantity
08/15/2000US6104774 Digital wave shaping circuit, frequency multiplying circuit, and external synchronizing method, and external synchronizing circuit
08/15/2000US6104643 Integrated circuit clock input buffer
08/15/2000US6104332 Absolute value circuit and method
08/15/2000US6104228 Phase aligner system and method
08/15/2000US6104225 Semiconductor device using complementary clock and signal input state detection circuit used for the same
08/15/2000US6104224 Delay circuit device having a reduced current consumption
08/15/2000US6104216 Differential amplifier having a reduced current dissipation
08/15/2000CA2072393C Variable delay device
08/10/2000WO2000014621A9 Synchronous polyphase clock distribution system
08/09/2000EP1026826A2 Comparator circuits
08/09/2000EP1025644A1 A master-slave delay locked loop for accurate delay of non-periodic signals
08/09/2000EP0890219B1 Circuit arrangement for regenerating an input signal containing digital data sequences
08/08/2000US6101197 Method and apparatus for adjusting the timing of signals over fine and coarse ranges