Patents
Patents for H03K 19 - Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits (41,996)
09/2008
09/09/2008US7423448 Radiation hardened logic circuit
09/04/2008WO2008105243A1 Dual-rail domino circuit, domino circuit, and logic circuit
09/04/2008WO2007149517A3 Circuit and method for power management
09/04/2008US20080215914 Self-reparable semiconductor and method thereof
09/04/2008US20080211563 Interface Circuit, Power Conversion Device, and Vehicle-Mounted Electric Machinery System
09/04/2008US20080211548 Semiconductor integrated circuit controlling output impedance and slew rate
09/04/2008US20080211543 4-Level Logic Decoder
09/04/2008US20080211542 Input buffer with wide input voltage range
09/04/2008US20080211541 Precision voltage level shifter based on thin gate oxide transistors
09/04/2008US20080211540 Programmable anti-fuse based on, e.g., zncds memory devices for fpga and other applications
09/04/2008US20080211539 Programmable matrix array with phase-change material
09/04/2008US20080211538 Flexible wrapper architecture for tiled networks on a chip
09/04/2008US20080211537 Open drain output circuit
09/04/2008US20080211536 Driver calibration methods and circuits
09/04/2008US20080211535 Pseudo-differential output driver with high immunity to noise and jitter
09/04/2008US20080211532 Circuit with control function and test method thereof
09/04/2008DE102008011789A1 Integrated circuit, has multiple partial circuits with substrate, and multiple multi-gate field-effect transistor power supply circuits that are electrically coupled with different voltage of selectable partial circuits
09/04/2008DE102008009950A1 Schaltkreis und Verfahren zum Umwandeln eines einendigen Signals in gedoppelte Signale Circuit and method for converting a single-ended signal in duplicated signals
09/04/2008DE102007009525A1 Konzept zum Erzeugen eines versorgungsspannungsabhängigen Taktsignals Concept for generating a supply voltage-gated clock signal
09/03/2008EP1965495A2 Method and switching device for control of at least one transistor in a driver circuit assembly
09/03/2008EP1964267A1 Semiconductor body, circuit arrangement having the semiconductor body and method
09/03/2008EP1964266A1 A method for multi-cycle clock gating
09/03/2008EP1554743A4 Method and apparatus for bootstrapping a programmable antifuse circuit
09/03/2008EP1118065B1 Circuit and method for authenticating the content of a memory location
09/03/2008CN101258679A Logic modules for semiconductor integrated circuits
09/03/2008CN101257301A Semiconductor device
09/03/2008CN101257300A Adjustable transistor body bias circuit
09/03/2008CN101257290A Annular voltage controlled oscillator
09/03/2008CN101257284A Semiconductor device
09/03/2008CN101256760A Starting up picture correcting apparatus and source electrode driver using the same
09/03/2008CN101256755A Driver circuit
09/03/2008CN100417023C Device for realizing pseudo-random code sequence generator self heeling
09/03/2008CN100417022C Semiconductor integrated circuit, method of manufacturing semiconductor integrated circuit, related circuit, instrument and program
09/03/2008CN100417021C Voltage level converter and continuous pulse generator
09/02/2008US7420535 Display
09/02/2008US7420397 Low-consumption inhibit circuit with hysteresis
09/02/2008US7420396 Universal logic gate utilizing nanotechnology
09/02/2008US7420395 Output buffer circuit and system including the output buffer circuit
09/02/2008US7420394 Latching input buffer circuit with variable hysteresis
09/02/2008US7420393 Single gate oxide level shifter
09/02/2008US7420392 Programmable gate array and embedded circuitry initialization and processing
09/02/2008US7420391 Circuit arrangement and method for operating a circuit arrangement
09/02/2008US7420390 Method and apparatus for implementing additional registers in field programmable gate arrays to reduce design size
09/02/2008US7420389 Clock distribution in a configurable IC
09/02/2008US7420388 Power gating techniques able to have data retention and variability immunity properties
08/2008
08/28/2008WO2008102450A1 Input/output circuit device
08/28/2008WO2007070886A3 Address transition detector for fast flash memory device
08/28/2008US20080209385 Mapping Programmable Logic Devices
08/28/2008US20080205110 Digital Magnetic Current Sensor and Logic
08/28/2008US20080204082 Apparatus And Method For Generating A Constant Logical Value In An Integrated Circuit
08/28/2008US20080204081 Clock gated circuit
08/28/2008US20080204080 Mobile circuit robust against input voltage change
08/28/2008US20080204079 Level shifting circuits for generating output signals having similar duty cycle ratios
08/28/2008US20080204078 Level shifter for preventing static current and performing high-speed level shifting
08/28/2008US20080204077 Level shifter
08/28/2008US20080204076 Integrated Circuit and a Method For Designing a Boundary Scan Super-Cell
08/28/2008US20080204075 Interfacing of circuits in an integrated electronic circuit
08/28/2008US20080204074 Dedicated interface architecture for a hybrid integrated circuit
08/28/2008US20080204073 Redundant configuration memory systems and methods
08/28/2008US20080204072 Programmable Logic Device
08/28/2008US20080204071 On-die termination circuit, method of controlling the same, and ODT synchronous buffer
08/28/2008US20080204070 Reduced power output buffer
08/28/2008US20080204069 Electronic Module With Organic Logic Circuit Elements
08/28/2008US20080204065 Fault tolerant selection of die on wafer
08/28/2008US20080203437 Semiconductor integrated circuit device with reduced leakage current
08/28/2008DE102008010472A1 Vorrichtung und Verfahren zum Erzeugen eines konstanten logischen Wertes in einem integrierten Schaltkreis Apparatus and method for generating a constant logic value in an integrated circuit
08/27/2008EP1961120A2 Method of producing and operating a low power junction field effect transistor
08/27/2008EP1961119A2 Address transition detector for fast flash memory device
08/27/2008EP1636903B1 Regenerative clock repeater
08/27/2008EP1364460B1 Interface circuit for a differential signal
08/27/2008CN101252354A Output stage circuit reducing transcend quantity
08/27/2008CN101252353A Shift buffer
08/27/2008CN101252348A Voltage controlled oscillator
08/27/2008CN100414840C Logic circuit device and working method of programable logic circuit
08/27/2008CN100414839C Control circuit and reconfigurable logic block
08/27/2008CN100414838C Negative voltage effective transmission circuit of standard logic process
08/27/2008CN100414837C Electronic driver circuit for generating circuit output signal provided for electric conductor
08/27/2008CN100414644C Voltage generating circuit
08/27/2008CN100414314C Integrated circuit having cell with fixed output voltage
08/26/2008US7418579 Component with a dynamically reconfigurable architecture
08/26/2008US7418283 Adiabatic quantum computation with superconducting qubits
08/26/2008US7417481 Controlling signal states and leakage current during a sleep mode
08/26/2008US7417469 Compensation for leakage current from dynamic storage node variation by the utilization of an automatic self-adaptive keeper
08/26/2008US7417468 Dynamic and differential CMOS logic with signal-independent power consumption to withstand differential power analysis
08/26/2008US7417467 Semiconductor integrated circuit
08/26/2008US7417465 N-domino output latch
08/26/2008US7417464 Bi-directional signal transmission system
08/26/2008US7417463 Wireline transmission circuit
08/26/2008US7417462 Variable external interface circuitry on programmable logic device integrated circuits
08/26/2008US7417461 Signal output circuit
08/26/2008US7417460 Multi-standard transmitter
08/26/2008US7417459 On-die offset reference circuit block
08/26/2008US7417458 Gate driving circuit and display apparatus having the same
08/26/2008US7417457 Scalable non-blocking switching network for programmable logic
08/26/2008US7417456 Dedicated logic cells employing sequential logic and control logic functions
08/26/2008US7417455 Programmable function generator and method operating as combinational, sequential and routing cells
08/26/2008US7417454 Low-swing interconnections for field programmable gate arrays
08/26/2008US7417453 System and method for dynamically executing a function in a programmable logic array
08/26/2008US7417452 Techniques for providing adjustable on-chip termination impedance
08/21/2008WO2008101095A2 Variable off-chip drive