Patents
Sitemap › H01 - Basic electric elements › H01L - Semiconductor devices; Electric solid state devices not otherwise provided for › H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
Patents for H01L 29 - Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. pn-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof (218,143)
05/2007
05/03/2007WO2005089115A3 Adaptive voltage control for performance and energy optimization
05/03/2007WO2005029556A3 Method of filling structures for forming via-first dual damascene interconnects
05/03/2007US20070101301 Simulation appartus, simulation method, and semiconductor device
05/03/2007US20070099402 Method for fabricating reliable semiconductor structure
05/03/2007US20070099400 Semiconductor circuit and method of fabricating the same
05/03/2007US20070099389 Capacitor layout technique for reduction of fixed pattern noise in a CMOS sensor
05/03/2007US20070099388 Source/Drain Extensions Having Highly Activated and Extremely Abrupt Junctions
05/03/2007US20070099386 Integration scheme for high gain fet in standard cmos process
05/03/2007US20070099378 Semiconductor device having align key and method of fabricating the same
05/03/2007US20070099374 Bicmos device and method of manufacturing a bicmos device
05/03/2007US20070099373 Method for manufacturing an integrated semiconductor transistor device with parasitic bipolar transistor
05/03/2007US20070099372 Device having active regions of different depths
05/03/2007US20070099368 Field effect transistor and method for manufacturing the same
05/03/2007US20070099367 ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN 110 Si UNDER BIAXIAL COMPRESSIVE STRAIN
05/03/2007US20070099360 Integrated circuits having strained channel field effect transistors and methods of making
05/03/2007US20070099352 Method for annealing silicon thin films and polycrystalline silicon thin films prepared therefrom
05/03/2007US20070099347 Array of cells including a selection bipolar transistor and fabrication method thereof
05/03/2007US20070099345 Method for producing through-contacts and a semiconductor component with through-contacts
05/03/2007US20070099338 Capacitor with a Dielectric Including a Self-Organized Monolayer of an Organic Compound
05/03/2007US20070099333 Thin-film transistor, method of producing thin-film transistor, electronic circuit, display, and electronic device
05/03/2007US20070099331 Hydrazine-free solution deposition of chalcogenide films
05/03/2007US20070099238 Enhancement of emission using metal coated dielectric nanoparticles
05/03/2007US20070097762 Semiconductor storage device, redundancy circuit thereof, and portable electronic device
05/03/2007US20070097241 Solis-state imaging device, method of driving same, and camera apparatus
05/03/2007US20070096647 Array panel
05/03/2007US20070096342 Method for reducing or eliminating semiconductor device wire sweep in a multi-tier bonding device and a device produced by the method
05/03/2007US20070096340 Electronic assembly having graded wire bonding
05/03/2007US20070096339 Junction structure of terminal pad and solder, semiconductor device having the junction structure, and method of manufacturing the semiconductor device
05/03/2007US20070096338 Semiconductor package having non-solder mask defined bonding pads and solder mask defined bonding pads, printed circuit board and semiconductor module having the same
05/03/2007US20070096337 Void-free circuit board and semiconductor package having the same
05/03/2007US20070096332 Electronic component, module, module assembling method, module identification method and module environment setting method
05/03/2007US20070096330 Semiconductor device with inclined through holes
05/03/2007US20070096329 Semiconductor device and manufacturing method of the same
05/03/2007US20070096328 Multilayered printed wiring board
05/03/2007US20070096327 Printed wiring board
05/03/2007US20070096325 Semiconductor apparatus
05/03/2007US20070096324 Metal during pattern for memory devices
05/03/2007US20070096323 Metal during pattern for memory devices
05/03/2007US20070096321 Conformal lining layers for damascene metallization
05/03/2007US20070096320 Semiconductor device
05/03/2007US20070096319 Method for fabricating and BEOL interconnect structures with simultaneous formation of high-k and low-k dielectric regions
05/03/2007US20070096317 Semiconductor device featuring electrode terminals forming superior heat-radiation system
05/03/2007US20070096316 Contact pad structure for flip chip semiconductor die
05/03/2007US20070096315 Ball contact cover for copper loss reduction and spike reduction
05/03/2007US20070096313 Semiconductor chip with post-passivation scheme formed over passivation layer
05/03/2007US20070096310 Semiconductor device
05/03/2007US20070096308 Semiconductor device
05/03/2007US20070096307 Semiconductor device
05/03/2007US20070096306 Semiconductor device and fabrication method thereof
05/03/2007US20070096304 Interconnects and heat dissipators based on nanostructures
05/03/2007US20070096263 Accessible chip stack and process of manufacturing thereof
05/03/2007US20070096262 Method for manufacturing nitride semiconductor substrate
05/03/2007US20070096261 Semiconductor device and manufacturing method thereof
05/03/2007US20070096259 Fabrication of bipolar transistor having reduced collector-base capacitance
05/03/2007US20070096256 Fully integrated floating power supply for high voltage technologies including n-epi biasing
05/03/2007US20070096255 High resistance cmos resistor
05/03/2007US20070096254 Multilayer ceramic capacitor with internal current cancellation and bottom terminals
05/03/2007US20070096253 Integrated capacitor with a high breakdown voltage
05/03/2007US20070096252 Multi-surfaced plate-to-plate capacitor and method of forming same
05/03/2007US20070096251 Semiconductor device and method of fabricating the same
05/03/2007US20070096250 Semiconductor device and method of manufacturing the same
05/03/2007US20070096249 Three-dimensionally integrated electronic assembly
05/03/2007US20070096248 Phase change memory cell
05/03/2007US20070096247 Semiconductor integrated circuit device and method of manufacturing the same
05/03/2007US20070096246 Semiconductor device
05/03/2007US20070096237 Design and fabrication of rugged fred, power mosfet or igbt
05/03/2007US20070096230 Magnetic memory cells and manufacturing methods
05/03/2007US20070096227 Wafer level package for surface acoustic wave device and fabrication method thereof
05/03/2007US20070096226 MOSFET dielectric including a diffusion barrier
05/03/2007US20070096225 Semiconductor device and method for forming the same
05/03/2007US20070096224 Semiconductor device and a method for manufacturing the same
05/03/2007US20070096222 Low voltage nanovolatile memory cell with electrically transparent control gate
05/03/2007US20070096220 HDP/PECVD methods of fabricating stress nitride structures for field effect transistors, and field effect transistors so fabricated
05/03/2007US20070096219 Lateral bipolar cmos integrated circuit
05/03/2007US20070096218 Eeprom array with well contacts
05/03/2007US20070096217 Mos transistors having inverted t-shaped gate electrodes and fabrication methods thereof
05/03/2007US20070096216 Manufacturing semiconductor circuit, corresponding semiconductor circuit, and associated design process
05/03/2007US20070096215 Transistor with dielectric stressor elements
05/03/2007US20070096211 Method of evaluating semiconductor device
05/03/2007US20070096210 Semiconductor device and method of forming the same
05/03/2007US20070096207 Semiconductor device and method for manufacturing the same
05/03/2007US20070096205 Power semiconductor device and method for manufacturing the same
05/03/2007US20070096204 Method for manufacturing semiconductor device
05/03/2007US20070096203 Recessed channel negative differential resistance-based memory cell
05/03/2007US20070096202 Semiconductor device and method for fabricating the same
05/03/2007US20070096201 Single mask scheme method and structure for integrating PMOS and NMOS transistors using strained silicon
05/03/2007US20070096200 Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory
05/03/2007US20070096199 Method of manufacturing symmetric arrays
05/03/2007US20070096198 Non-volatile memory cells and method for fabricating non-volatile memory cells
05/03/2007US20070096197 Non-volatile memory devices including etching protection layers and methods of forming the same
05/03/2007US20070096196 Fin field effect transistor arrangement and method for producing a fin field effect transistor arrangement
05/03/2007US20070096195 Technique for providing multiple stress sources in nmos and pmos transistors
05/03/2007US20070096194 Technique for strain engineering in si-based transistors by using embedded semiconductor layers including atoms with high covalent radius
05/03/2007US20070096193 Non-volatile memory device with tensile strained silicon layer
05/03/2007US20070096192 Capacitor of semiconductor device and method of fabricating the same
05/03/2007US20070096191 Coupling capacitor and semiconductor memory device using the same
05/03/2007US20070096190 Interconnect line selectively isolated from an underlying contact plug
05/03/2007US20070096189 Semiconductor device
05/03/2007US20070096188 Method of manufacturing semiconductor device
05/03/2007US20070096187 Semiconductor device including source strapping line
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