Patents
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
07/2005
07/19/2005US6920080 Methods for generating output control signals in synchronous semiconductor memory devices and related semiconductor memory devices
07/19/2005US6920075 Amplifier for reading storage cells with exclusive-OR type function
07/19/2005US6920074 Method for reading a memory cell in a semiconductor memory, and semiconductor memory
07/19/2005US6920073 Row redundancy circuit and repair method
07/19/2005US6920071 Semiconductor integrated circuit device
07/19/2005US6920068 Semiconductor memory device with modified global input/output scheme
07/19/2005US6919745 Ring-resister controlled DLL with fine delay line and direct skew sensing detector
07/14/2005WO2005064616A1 Synchronization devices having input/output delay model tuning elements
07/14/2005US20050154942 Disk array system and method for controlling disk array system
07/14/2005US20050154853 Memory device and method of operation of a memory device
07/14/2005US20050154842 Address control system for a memory storage device
07/14/2005US20050154817 Method of operation and controlling a memory device
07/14/2005US20050154763 Segmentation metadata for audio-visual content
07/14/2005US20050152448 Signaling for entry point frames with predicted first field
07/14/2005US20050152231 Conversion device of MP3
07/14/2005US20050152211 DRAM controller and DRAM control method
07/14/2005US20050152210 Synchronous dynamic random access memory devices having dual data rate 1 (DDR1) and DDR2 modes of operation and methods of operating same
07/14/2005US20050152209 Synchronous semiconductor memory devices and data strobe input buffers with an input buffer circuit and a detection circuit for buffering data thereto
07/14/2005US20050152205 Semiconductor memory
07/14/2005US20050152203 Semiconductor memory device and method of arranging a decoupling capacitor thereof
07/14/2005US20050152202 Portable data storage apparatus
07/14/2005US20050152201 Semiconductor memory device and control method thereof
07/14/2005US20050152200 Semiconductor memory having variable memory size and method for refreshing the same
07/14/2005US20050152199 DRAM-based CAM cell with shared bitlines
07/14/2005US20050152198 Logical operation circuit and logical operation method
07/14/2005US20050152197 Camera interface and method using DMA unit to flip or rotate a digital image
07/14/2005US20050152196 Sense amplifier circuit and read/write method for semiconductor memory device
07/14/2005US20050152195 Method and device for testing a sense amp
07/14/2005US20050152170 Bit cell array for preventing coupling effect in read only memory
07/14/2005US20050151561 Output driver for use in semiconductor device
07/14/2005DE202005007170U1 Portable electronic device for storage of sensitive device, e.g. PINs, has a touch sensitive sensor which, when correctly contacted, triggers operation of the device
07/14/2005DE202005003446U1 Packing for memory cards has double capacity/two substrates with micro-controllers linked by a card holder in a symmetrically overlapping position
07/14/2005DE10358324A1 Leistungstransistorzelle und Leistungstransistorbauelement mit Schmelzsicherung Power transistor cell and power transistor device with fuse
07/14/2005DE10345825A1 Comparison method for comparing programmable integrated circuit units, uses two memory units for use-specific data with second data being non-volatile
07/14/2005DE102004059035A1 Einprägeunterdrückungs-Schaltungsschema Einprägeunterdrückungs circuit diagram
07/14/2005DE10157874B4 Vorrichtung zum Zuführen von Steuersignalen zu Speichereinheiten und dafür angepasste Speichereinheit Device for supplying control signals to memory devices, and that are adapted to memory unit
07/14/2005DE10149192B4 Vorrichtung zum Erzeugen von Speicher-internen Befehlssignalen aus einem Speicheroperationsbefehl Apparatus for generating memory-internal command signals from a memory operation command
07/13/2005EP1553523A2 Compression using Discrete Cosine Transform (DCT)
07/13/2005EP1553500A1 Method and apparatus for indication of valid data
07/13/2005EP1552314A2 Sense amplifier with configurable voltage swing control
07/13/2005CN1639797A Increasing a refresh period in a semiconductor memory device
07/13/2005CN1638974A Device, system and method for data exchange
07/13/2005CN1638278A Method and apparatus to reduce bias temperature instability (bti) effects
07/13/2005CN1638224A Semiconductor device and semiconductor device module
07/13/2005CN1638121A 半导体集成电路装置 The semiconductor integrated circuit device
07/13/2005CN1637951A Semiconductor readout circuit
07/13/2005CN1637948A Set programming methods and write driver circuits for a phase-change memory array
07/13/2005CN1637947A Semiconductor memory device and data read and write method thereof
07/13/2005CN1637946A Internal voltage generating circuit in semiconductor memory device
07/13/2005CN1637945A Power-up circuit semiconductor memory device
07/13/2005CN1637944A Power-up circuit semiconductor memory device
07/13/2005CN1637943A Power-up circuit in semiconductor memory device
07/13/2005CN1637942A Semiconductor memory device with optimum refresh cycle according to temperature variation
07/13/2005CN1637940A Semiconductor memory device for high speed data access
07/13/2005CN1637939A Semiconductor memory apparatus
07/13/2005CN1637938A 半导体存储装置 The semiconductor memory device
07/13/2005CN1637937A 半导体存储装置 The semiconductor memory device
07/13/2005CN1637935A Semiconductor memory device having external data load signal and serial-to-parallel data prefetch method thereof
07/13/2005CN1637933A Imprint suppression circuit scheme
07/13/2005CN1637926A Addressing circuit for a cross-point memory array including cross-point resistive elements
07/13/2005CN1637925A Semiconductor device card providing multiple working voltages
07/13/2005CN1637731A DRAM controller and DRAM control method
07/13/2005CN1637719A Data storage apparatus, data storage control apparatus, data storage control method, and data storage control program
07/13/2005CN1210804C Nonvolatile semiconductor memory device
07/12/2005US6918048 System and method for delaying a strobe signal based on a slave delay base and a master delay adjustment
07/12/2005US6918047 Apparatus for high data rate synchronous interface using a delay locked loop to synchronize a clock signal and a method thereof
07/12/2005US6918046 High speed interface device for reducing power consumption, circuit area and transmitting/receiving a 4 bit data in one clock period
07/12/2005US6917660 Adaptive de-skew clock generation
07/12/2005US6917562 Semi-conductor component with clock relaying device
07/12/2005US6917561 Memory controller and method of aligning write data to a memory device
07/12/2005US6917556 Static memory cell having independent data holding voltage
07/12/2005US6917555 Integrated circuit power management for reducing leakage current in circuit arrays and method therefor
07/12/2005US6917552 Semiconductor device using high-speed sense amplifier
07/12/2005US6917550 Semiconductor memory device
07/12/2005US6917549 Integrated memory and method for operating it
07/12/2005US6917546 Memory device and memory system
07/12/2005US6917545 Dual bus memory burst architecture
07/12/2005US6917543 Flash memory for improving write access time
07/12/2005US6917541 Nonvolatile semiconductor memory device
07/12/2005US6917535 Column select circuit of ferroelectric memory
07/12/2005US6917534 Offset compensated sensing for magnetic random access memory
07/12/2005US6917228 Delay locked loop circuit with time delay quantifier and control
07/12/2005US6916677 Magnetic storage apparatus having dummy magnetoresistive effect element and manufacturing method thereof
07/07/2005WO2005060465A2 Low-power compiler-programmable memory with fast access timing
07/07/2005WO2004053879A3 Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
07/07/2005US20050149788 Methods of testing semiconductor memory devices in a variable CAS latency environment and related semiconductor test devices
07/07/2005US20050149785 Apparatus and method for testing a flash memory unit using stress voltages
07/07/2005US20050149782 Semiconductor memory repair methodology using quasi-non-volatile memory
07/07/2005US20050149687 Device identification using a memory profile
07/07/2005US20050149665 Scratchpad memory
07/07/2005US20050149662 System having a plurality of integrated circuit buffer devices
07/07/2005US20050146980 Fixed phase clock and strobe signals in daisy chained chips
07/07/2005US20050146979 Asynchronously-resettable decoder with redundancy
07/07/2005US20050146976 Semiconductor memory device
07/07/2005US20050146975 Method and apparatus for multiple row caches per bank
07/07/2005US20050146974 Method and apparatus for multiple row caches per bank
07/07/2005US20050146973 Device, system and method for reducing power in a memory device during standby modes
07/07/2005US20050146972 Low power semiconductor memory device
07/07/2005US20050146970 Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used
07/07/2005US20050146969 Semiconductor memory apparatus