Patents
Sitemap › G11 - Information storage › G11C - Static stores › G11C 7 - Arrangements for writing information into, or reading information out from, a digital store
Patents for G11C 7 - Arrangements for writing information into, or reading information out from, a digital store (53,197)
09/2005
09/01/2005US20050193183 Method and apparatus for initializing dynamic random access memory (DRAM) devices
09/01/2005US20050193163 Integrated circuit buffer device
09/01/2005US20050192689 Recording and/or reproducing apparatus and recording apparatus
09/01/2005US20050192686 Semiconductor memory card, playback apparatus, recording apparatus, playback method, recording method, and computer-readable recording medium
09/01/2005US20050191029 Editing apparatus and editing method
09/01/2005US20050190635 Memory device having conditioning output data
09/01/2005US20050190634 Memory system using simultaneous bi-directional input/output circuit on an address bus line
09/01/2005US20050190631 Method for bus capacitance reduction
09/01/2005US20050190625 Semiconductor memory
09/01/2005US20050190624 Semiconductor device
09/01/2005US20050190623 Position based erase verification levels in a flash memory device
09/01/2005US20050190622 System and method for communicating information to a memory device using a reconfigured device pin
09/01/2005US20050190621 Nonvolatile semiconductor memory device using ferroelectric capacitor
09/01/2005US20050190619 Communication system
09/01/2005US20050190618 Semiconductor memory device with reliable fuse circuit
09/01/2005US20050190616 Content distribution systems and methods
09/01/2005US20050190614 Novel radio frequency (RF) circuit board topology
09/01/2005US20050190602 Semiconductor integrated circuit adapted to output pass/fail results of internal operations
09/01/2005US20050190598 Non-volatile memory technology compatible with 1T-RAM process
09/01/2005US20050190593 Magnetoelectronic memory element with inductively coupled write wires
09/01/2005US20050190591 Dynamic semiconductor memory device
09/01/2005US20050190588 Semiconductor device
09/01/2005US20050189977 Double-edge-trigger flip-flop
09/01/2005DE102005004338A1 Phase-change random access memory cell device, has write driver control circuit coupled to address decoder to vary pulse width and pulse count of pulse currents according to load between write driver and cell selected by decoder
09/01/2005DE102004015318B3 Input stage for electronic circuit for receiving, evaluating input signal, passing to subsequent stage has control circuit that activates one or other receiving stage depending on current drains of both stages for respective input signal
09/01/2005DE102004007620A1 Vorladeschaltkreis für die Inbetriebnahme eines DC-DC-Wandlers zur Spannungserhöhung Pre-charge circuit for the commissioning of a DC-DC converter to increase the voltage
09/01/2005DE102004006254A1 Schaltungsanordnung zur Erzeugung eines Rücksetzsignals nach einem Absinken und Wiederansteigen einer Versorgungsspannung Circuit arrangement for generating a reset signal after a fall and re-rise of a supply voltage
09/01/2005DE102004005666A1 High frequency arrangement for data medium e.g. chip card, has semiconductor body with charge storage made using trench technology and two contact points that are connected to respective pins of another body having integrated circuit
08/2005
08/31/2005EP1568037A1 Improved pre-charge method for reading a non-volatile memory cell
08/31/2005EP1568036A1 Sdram address mapping optimized for two-dimensional access
08/31/2005EP1567938A2 Memory system comprising a plurality of memory controllers and method for synchronizing the same
08/31/2005EP1374244B1 A method of synchronizing read timing in a high speed memory system
08/31/2005EP0910898A4 Selective recall and preservation of continuously recorded data
08/31/2005CN2722386Y Multi-media player
08/31/2005CN1662996A 半导体存储器 Semiconductor memory
08/31/2005CN1662993A Efficient read/write methods for streamline memory
08/31/2005CN1661724A Dynamic semiconductor memory device
08/31/2005CN1661723A Semiconductor integrated circuit
08/31/2005CN1661722A 半导体器件 Semiconductor devices
08/31/2005CN1661721A Data circuit structure in high-order local efficiency
08/31/2005CN1661545A Audio playing device
08/31/2005CN1217414C Semiconductor device
08/31/2005CN1217266C Memory address producing device, moving station and data read/write method
08/30/2005US6938143 Dynamically adaptive buffer mechanism
08/30/2005US6938142 Multi-bank memory accesses using posted writes
08/30/2005US6938117 Tri-stating output buffer during initialization of synchronous memory
08/30/2005US6937538 Asynchronously resettable decoder for a semiconductor memory
08/30/2005US6937535 Semiconductor memory device with reduced data access time
08/30/2005US6937534 Integrated circuit memory device including delay locked loop circuit and delay locked loop control circuit and method of controlling delay locked loop circuit
08/30/2005US6937533 Semiconductor integrated circuit provided with semiconductor memory circuit having redundancy function and method for transferring address data
08/30/2005US6937530 Delay locked loop “ACTIVE Command” reactor
08/30/2005US6937529 Semiconductor memory device performing reliable data sensing
08/30/2005US6937527 High reliability triple redundant latch with voting logic on each storage node
08/30/2005US6937515 Semiconductor memory device
08/30/2005US6937512 Nonvolatile semiconductor memory device with a ROM block settable in the write or erase inhibit mode
08/30/2005US6937504 Selecting a magnetic memory cell write current
08/30/2005US6937499 Non-destructive readout
08/30/2005US6937495 Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics
08/30/2005US6937485 Duty ratio detecting apparatus with small return time
08/30/2005US6937223 Driver having a storage device, electro-optical device using the driver, and electronic apparatus
08/30/2005US6937085 Sense amplifier based voltage comparator
08/30/2005US6937074 Power-up signal generator in semiconductor device
08/30/2005US6937052 Sensing services and sensing circuits
08/25/2005WO2005078735A1 Semiconductor memory
08/25/2005WO2005078734A1 Dll circuit
08/25/2005WO2005078731A1 Semiconductor memory
08/25/2005WO2005077025A2 Secured phase-change devices
08/25/2005US20050188150 Method and apparatus for providing a memory with write enable information
08/25/2005US20050187724 Frequency measuring circuits including charge pumps and related memory devices and methods
08/25/2005US20050186934 Semiconductor integrated circuit
08/25/2005US20050186326 High activity, spatially distributed radiation source for accurately simulating semiconductor device radiation environments
08/25/2005US20050185804 Recording and/or reproducing apparatus and recording apparatus
08/25/2005US20050185803 Recording and/or reproducing apparatus and recording apparatus
08/25/2005US20050185572 Fast reading, low consumption memory device and reading method thereof
08/25/2005US20050185500 Domain crossing device
08/25/2005US20050185498 Timing calibration pattern for SLDRAM
08/25/2005US20050185497 Semiconductor memory device
08/25/2005US20050185493 Data transfer method and system
08/25/2005US20050185492 Dynamic random access memory having at least two buffer registers and method for controlling such a memory
08/25/2005US20050185490 Voltage regulator and method of manufacturing the same
08/25/2005US20050185489 Dynamic data restore in thyristor-based memory device
08/25/2005US20050185488 Semiconductor data storage apparatus
08/25/2005US20050185487 Digitally controlled oscillator circuit
08/25/2005US20050185486 Ferroelectric memory devices including protection adhesion layers and methods of forming the same
08/25/2005US20050185484 Semiconductor memory device having test mode for data access time
08/25/2005US20050185483 Semiconductor memory storage device and its redundant method
08/25/2005US20050185482 Semiconductor memory storage device and a redundancy control method therefor
08/25/2005US20050185481 Redundancy relieving circuit
08/25/2005US20050185480 Dynamically activated memory controller data termination
08/25/2005US20050185479 Method and device for saving and setting a circuit state of a microelectronic circuit
08/25/2005US20050185474 Semiconductor integrated circuit
08/25/2005US20050185449 Nonvolatile data storage apparatus
08/25/2005US20050185442 Memory device having terminals for transferring multiple types of data
08/25/2005US20050184811 Semiconductor integrated circuit
08/25/2005DE69233384T2 Nicht-flüchtiger Halbleiterspeicher A non-volatile semiconductor memory
08/25/2005DE4439775B4 Bus-Interface-Schaltung für einen FIFO-Speicher Bus interface circuit for a FIFO memory
08/25/2005DE4435649B4 Dateneingabepuffer für eine Halbleiterspeichervorrichtung Data input buffer for a semiconductor memory device
08/25/2005DE102005003863A1 Speichervorrichtung mit Nicht-Variabler Schreiblatenz Memory device with non-variable write latency
08/25/2005DE102004004808A1 Maintenance of the state of a microelectronic circuit, in which certain circuit sections can be turned off, whereby a scan chain used for circuit testing is also used to collect register contents and then shift them into memory
08/25/2005DE102004004091A1 Vorrichtung zur Verwendung bei der Synchronisation von Taktsignalen, sowie Taktsignal-Synchronisationsverfahren Apparatus for use in the synchronization of clock signals, and clock signal synchronization method
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